scope:

This specification covers the detail requirements for monolithic silicon, complimentary oxide insulated silicon gate semiconductor, semicustom (gate array) devices. Two product assurance classes (B and S) and a choice of case outlines and lead finishes are provided for each type, and are reflected in the complete Part or Identifying Number (PIN).

Customizations (personalizations) for each design, including circuit organization, electrical performance characteristics, and test conditions, shall be specified in an Altered Item Drawing (AID) (see 3.2 herein).

The PIN shall be in accordance with MIL-M-38510, and as specified herein.

The device types (total number of usable gates) and circuit organization, shall be as identified in the specific AID and as follows:

Device type Circuit 01 0 - 1,000 gate array 02 1,001 - 2,000 gate array 03 2,001 - 3,000 gate array 04 3,001 - 4,000 gate array 05 4,001 - 5,000 gate array 06 5,001 - 6,000 gate array 07 6,001 - 7,000 gate array 08 7,001 - 8,000 gate array 09 8,001 - 9,000 gate array 10 9,001 -10,000 gate array 11 10,001 -11,000 gate array 12 11,001 -12,000 gate array 13 12,001 -15,000 gate array 14 15,001 -25,000 gate array 15 25,001 -35,000 gate array 16 35,001 -45,000 gate array 17 45,001 -55,000 gate array 18 55,001 -65,000 gate array 19 65,001 -75,000 gate array 20 75,001 -85,000 gate array

The device class shall be the product assurance level as defined in MIL-M-38510. Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Laboratory (RL/ERDS), Griffiss AFB, NY 13441-5700, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

The case outlines and letters shell be in accordance with MIL-M-38510, appendix C.

Outline Manufacturers letter Case outline (see table V) M 144-terminal, leaded chip carrier (see figure 1) B N P-BE (100-pin, square pin grid array) F,H T P-BD (108-pin, square pin grid array) F U P-BF (132-pin, square pin grid array) F X P-BE (124-pin, square pin grid array) H Y 132-terminal, leaded chip carrier (see figure 1) B Z 196-terminal, leaded chip carrier (see figure 1) B

Supply Voltage range- - - - - - - - - - - - - - - - - - - - −0.3 V dc to +7.0 V dc DC input, dc output voltage ranges (V_IN, V_OUT) - - - - - - −0.3 V dc to (V_DD +0.3 V dc) Storage temperature range - - - - - - - - - - - - - - - - - −65°C to +150°C Maximum junction temperature (T_J) - - - - - - - - - - - - - +175°C Thermal resistance, junction-to-case (θ_JC): M, Y, and Z - - - - - - - - - - - - - - - - - - - - - - 10°C/W All others - - - - - - - - - - - - - - - - - - - - - - - See MIL-M-38510, appendix C

Supply voltage (V_DD)- - - - - - - - - - - - - - - - - - - - 4.5 V dc to 5.5 V dc DC input voltage- - - - - - - - - - - - - - - - - - - - - - 0 V dc to V_DD Case operating temperature range (T_C) - - - - - - - - - - - −55°C to +125°C

intended Use:

Microcircuits conforming to this specification are intended for use for Government microcircuit applications (original equipment), design applications, and logistic purposes.