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NPFC - MIL-M-38510/600

MICROCIRCUITS, DIGITAL, BIPOLAR, SEMICUSTOM (GATE ARRAY) DEVICES, MONOLITHIC SILICON

active, Most Current
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Organization: NPFC
Publication Date: 27 February 1987
Status: active
Page Count: 16
scope:

This specification covers the detail requirements for monolithic silicon, Bipolar, semicustom (gate array) devices. Two product assurance classes (B and S) and a choice of case outline/lead finish are provided for each type, and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510, and as specified herein.

The device type (total number of usable gates) and circuit organization shall be as identified in the specific altered item drawing (AID) and as follows:

Device type Circuit 01 ≤ 1000 gate, gate array 02 ≤ 3500 gate, gate array 03 ≤ 5000 gate, gate array

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline and letter shall be in accordance with MIL-M-38510, appendix C.

Letter Case outline Manufacturer X P-AF (148-pin), square pin grid array A, B

Current mode logic (CML) supply voltage - - - 6.0 V dc TTL supply voltage- - - - - - - - - - - - - - 7.0 V dc Supply voltage range VCC- - - - - - - - - - - −0.5 V dc to 7.0 V dc Supply voltage range VEE- - - - - - - - - - - +0.5 V dc to −7.0 V dc Input voltage range - - - - - - - - - - - - - VEE to VCC Input current continuous- - - - - - - - - - - −30 mA to 1.0 mA Voltage applied to open-collector outputs in off-state- - - - - - - - - - - - - - - - −0.5 V dc to 7.0 V dc Thermal resistance, junction-to-case (θJC)- - 12°C/W Junction temperature (TJ) - - - - - - - - - - +140°C Maximum power dissipation - - - - - - - - - - 14 W

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB NY 13441-5700, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

VCC1 CML logic supply voltage- - 2.97 minimum to 3.63 maximum V dc (reduced power) VCC1 CML logic supply voltage- - 4.5 minimum to 5.5 maximum V dc VCC2 TTL I/O supply voltage- - - 4.5 minimum to 5.5 maximum V dc VEE1 (reduced) CML supply voltage- - - - - −3.63 minimum to −2.97 maximum V dc VEE1 (ECL 100K) CML supply voltage- - - - - −4.95 minimum to −4.05 maximum V dc VEE1 (ECL 10K) CML supply voltage- - - - - −5.72 minimum to −4.68 maximum V dc TC Case operating temperature- −55°C to +125°C

intended Use:

Microcircuits conforming to this specification are intended for use for Government microcircuit applications (original equipment), design applications, and logistic purposes.

Document History

November 30, 2021
Microcircuits, Digital, Bipolar, Semicustom (Gate Array) Devices, Monolithic Silicon
A description is not available for this item.
February 15, 2012
Microcircuits, Digital, Bipolar, Semicustom (Gate Array) Devices, Monolithic Silicon
A description is not available for this item.
May 9, 2007
MICROCIRCUITS, DIGITAL, BIPOLAR, SEMICUSTOM (GATE ARRAY) DEVICES, MONOLITHIC SILICON
A description is not available for this item.
July 23, 2002
MICROCIRCUITS, DIGITAL, BIPOLAR, SEMICUSTOM (GATE ARRAY) DEVICES, MONOLITHIC SILICON
A description is not available for this item.
August 9, 1996
MICROCIRCUITS, DIGITAL, BIPOLAR, SEMICUSTOM (GATE ARRAY) DEVICES, MONOLITHIC SILICON
A description is not available for this item.
November 9, 1989
MICROCIRCUITS, DIGITAL, BIPOLAR, SEMICUSTOM (GATE ARRAY) DEVICES, MONOLITHIC SILICON
A description is not available for this item.
February 5, 1988
MICROCIRCUITS, DIGITAL, BIPOLAR, SEMICUSTOM (GATE ARRAY) DEVICES, MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/600
February 27, 1987
MICROCIRCUITS, DIGITAL, BIPOLAR, SEMICUSTOM (GATE ARRAY) DEVICES, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, Bipolar, semicustom (gate array) devices. Two product assurance classes (B and S) and a choice of case outline/lead finish...

References

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