JEDEC JESD 248
DDR4 NVDIMM-N Design Standard Revision 1.0
| Organization: | JEDEC |
| Publication Date: | 1 September 2016 |
| Status: | inactive |
| Page Count: | 47 |
scope:
This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash. NVDIMM-N modules adhere to the Byte Addressable Energy Backed Interface Standard, JESD245, that provides detailed logical behavior, interface, and register definitions. These DDR4 NVDIMM-N modules are intended for use as main memory or storage when installed in PCs.
System interface constraints are included which provide an initial basis for DDR4 NVDIMM-N and LR NVDIMM-N designs. Modifications to these constraints may be required to meet all system timing, signal integrity and thermal requirements for PC4-1600, PC4-1866, PC4-2133, PC4-2400, PC4-2666 and PC4-3200 support. All DDR4 NVDIMM-N implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design.
An additional lower voltage of TBD is defined. PC4L is used to reference DIMMs capable of operation at this voltage level. The annex for each raw card will have specific entries to indicate DIMM operation at PC4 and PC4L voltage levels. This standard follows the JEDEC standard DDR4 component standard (refer to JEDEC standard JESD79-4, at www.jedec.org).
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