JEDEC JESD 22-B106
Resistance to Solder Shock for Through-Hole Mounted Devices
|Publication Date:||1 November 2016|
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement)
This test method shall not be used to simulate wave soldering of surface mount device packages that are glued onto the same side of the board as the solder wave and are fully submerged into the solder wave. The test method for simulating SMT devices through the wave is JESD22-A111, Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices.
In order to establish a standard test procedure for the most reproducible methods, the solder dip method is used because of its more controllable conditions. This procedure will determine whether devices are capable of withstanding the soldering temperature encountered in printed wiring board assembly operations, without degrading their electrical characteristics or internal connections. This test is destructive and may be used for qualification, lot acceptance and as a product monitor.