Standard Test Interface Language (STIL) for Digital Test Vector Data
|Publication Date:||1 November 2007|
|ICS Code (Electrical and electronic testing):||19.080|
|ICS Code (Industrial automation systems):||25.040|
This standard defines a test description language that:
a) Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment (ATE) environments;
b) Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT);
c) Supports the volume of test vector data generated from structured tests such as scan/automatic test pattern generation (ATPG), integral test techniques such as built-in self test (BIST), and functional test specifications for IC designs and their assemblies, in a format optimized for application in ATE environments.
In setting the scope for any standard, some issues are defined to not be pertinent to the initial project. The following is a partial list of issues that were dropped from the scope of this initial project:
- Levels: A key aspect of a digital test program is the ability to establish voltage and current parameters (levels) for signals under test. Level handling is not explicitly defined in the current standard, as this information is both compact (not presenting a transportation issue) and commonly established independently of digital test data, requiring different support mechanisms outside the current scope of this standard. Termination values may affect levels.
- Datalogging mechanisms, formatting, and control usually are not defined as part of this current standard.
- Parametric tests are not defined as an integral part of this standard, except for optional pattern labels that identify potential locations for parametric tests, such as IDDQ tests or alternating current (AC) timing tests.
- Program flow: Test sequencing and ordering are not defined as part of the current standard except as necessary to define collections of digital patterns meant to execute as a unit.
- Binning constructs are not part of the current standard.
- Analog or mixed-signal test: While this is an area of concern for many participants, at this point transfer of analog test data does not contribute to the same transportation issue seen with digital data.
- Algorithmic pattern constructs (such as sequences commonly used for memory test) are not currently defined as part of the standard.
- Parallel test/multisite test constructs are not an integral part of the current environment.
- User input and user control/options are not part of the current standard.
- Characterization tools, such as shmoo plots, are not defined as part of the current standard.
This standard addresses a need in the integrated circuit (IC)1 test industry to define a standard mechanism for transferring the large volumes of digital test data from the generation environment through to test. The environment today contains unique output formats of existing CAE tools, individual test environments of IC manufacturers, and proprietary IC ATE input interfaces. As each of these three arenas solves individual problems, together they have created a morass of interfaces, translators, and software environments that provide no opportunity to leverage common goals and result in much wasted efforts re-engineering solutions. As device density increases, the magnitude of test data threatens to shift the test bottleneck from the generation process to the processes necessary solely to maintain and transport this data. These two factors threaten to eliminate any productive work performed in this area unless a viable standard is defined.
With a common standard for CAE and IC ATE environments, the generation, movement, and processing of this test data is greatly facilitated. This standard also allows for immediate access to test equipment supporting this standard, which benefits both ATE and IC vendors reviewing this equipment.
This standard also serves as a catalyst for the development of a set of standard third party interface tools to both test and design aspects of IC device generation