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DLA - DSCC-VID-V62/12601 REV A

MICROCIRCUIT, DIGITAL-LINEAR, ENHANCED, LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 16 April 2018
Status: inactive
Page Count: 11
scope:

This drawing documents the general requirements of a high performance enhanced, low input voltage mode synchronous buck controller microcircuit, with an operating temperature range of -55°C to +125°C.

Document History

DSCC-VID-V62/12601 REV B
September 18, 2023
MICROCIRCUIT, DIGITAL-LINEAR, ENHANDCED, LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER, MONOLITHIC SILICON
Scope. This drawing documents the general requirements of a high performance enhanced, low input voltage mode synchronous buck controller microcircuit, with an operating temperature range of -55ºC...
DSCC-VID-V62/12601 REV A
April 16, 2018
MICROCIRCUIT, DIGITAL-LINEAR, ENHANCED, LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance enhanced, low input voltage mode synchronous buck controller microcircuit, with an operating temperature range of -55°C to +125°C.
DSCC-VID-V62/12601
December 14, 2012
MICROCIRCUIT, DIGITAL-LINEAR, ENHANCED, LOW INPUT VOLTAGE MODE SYNCHRONOUS BUCK CONTROLLER, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance enhanced, low input voltage mode synchronous buck controller microcircuit, with an operating temperature range of -55°C to +125°C.

References

This document references:
JEP95 JEDEC STD NO. 95-1 - JEDEC Standard No. 95-1 Section 4 Design Guidelines
Published by JEDEC on March 1, 1997
INTRODUCTION History JEDEC REGISTERED AND STANDARD OUTLINES FOR SEMICONDUCTOR DEVICES, JEDEC PUBLICATION 95, is the official JEDEC Publication that contains the registered or standard mechanical...
This document references:
JEDEC JESD 51-2 - Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
Published by JEDEC on January 1, 2008
This document outlines the environmental conditions necessary to ensure accuracy and repeatability for a standard junction-to-ambient thermal resistance measurement in natural convection.
This document references:
JEDEC JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Published by JEDEC on February 1, 1999
This fixturing further defines the environment for thermal test of packaged microelectronic devices. Its function is to provide an alternate mounting surface for the analysis of heat flow in...
This document references:
JEDEC JESD 51-8 - Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board
Published by JEDEC on October 1, 1999
This specification should be used in conjunction with the overview document JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) [1] and the electrical...
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