scope:

This report is intended to document the various test patterns used to qualify and troubleshoot both DS0 (56/64 kbit/s) & Synchronous Digital Data circuits. Reviewed in this report are present day industry practices and recommendations for the application of specific patterns for "stressing" circuits and circuit components both prior to service and in the trouble isolation mode.

Organization of the report

Following some basic acronyms and definitions in Section 2, Sections 3&4 provide background on the need for multiple DS0 test signals. Section 5 describes the placement of test signals on the DS0 path, and Sections 6&7 explain the use of specific test patterns and describe the pattern elements. Section 8 covers test patterns that are available for use but have not been approved in Standards or other industry bodies.