scope:

This specification covers the detail requirements for monolithic silicon, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510, and as specified herein.

The device type shall be as follows:

Device type Circuit 01 Dual 4-stage/dual 5-stage static shift register 02 8-stage synchronous parallel or serial input/serial output static shift register 03 Dual 4-stage serial input/parallel output static shift register. 04 8-stage asynchronous parallel input/serial output or synchronous serial input/serial output static shift register. 05 64-stage static shift register. 06 8-stage bidirectional parallel/serial input/output bus register. 51 Dual 4-stage/dual 5-stage static shift register. 52 8-stage synchronous parallel or serial input/serial output static shift register. 53 Dual 4-stage serial input/parallel output static shift register. 54 8-stage asynchronous parallel input/serial output or synchronous serial input/serial output static shift register. 55 64-stage static shift register. 56 8-stage bidirectional parallel/serial input/ output bus register.

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) A F-1 (14-lead, ¼" × ¼"), flat package C D-1 (14-lead, ¼" × ¾"), dual-in-line package

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: NASA Parts Project Office, Code 311.A, NASA/Goddard Space Flight Center, Greenbelt, MD 20771 by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

D F-2 (14-lead, ¼" × ⅜"), flat package E $ D-2 (16-lead, ¼" × ⅞"), dual-in-line package F F-5 (16-lead, ¼" × ⅜"), flat package J D-3 (24-lead, ½" × 1-¼"), dual-in-line package K F-6 (24-lead, ⅜" × ⅝"), flat package X F-1 (14-lead, ¼" × ¼"), flat package, except A dimensions = 0.1" (2.54 mm max.) Y F-2 (14-lead, ¼" × ⅜"), flat package, except A dimensions = 0.1" (2.54 mm max.) Z F-5 (16-lead, ¼" × ⅜"), flat package, except A dimensions = 0.1" (2.54 mm max.) U F-6 (24-lead, ⅜" × ⅝"), flat package, except A dimension = 0.1" (2.54 mm max.)

NOTES

1. As an exception to 3.5.6.2.3 of MIL-M-38510, for case outlines X, Y, Z, and U only, the leads of bottom brazed ceramic packages (i.e., configuration 2 of case outlines F-1, F-2, F-5, and F-6) may have electroless nickel undercoating which shall be 50 to 200 microinches (1.27 to 5.08 μm) thick provided the lead finish is hot solder dip (i.e., finish letter A) and provided that, after any lead forming, an additional hot solder dip coating is applied which shall extend from the outer tip of the lead to no more than 0.015 inch (0.38 mm) from the package edge.

2. For bottom or side brazed packages, case outlines X, Y, Z, and U only, the S₁ dimension may go to .000 inch (.00 mm) minimum.

Supply voltage range (V_DD - V_SS) Device types 01-06 - - - - - - - - −0.5 V dc to +15.5 V dc Device types 51-56 - - - - - - - - −0.5 V dc to +18.0 V dc Input current (each input) - - - - - ±10 mA Input voltage range- - - - - - - - - (V_SS − 0.5 V) ≤ V_I ≤ (V_DD +0.5 V) Storage temperature range- - - - - - −65°C to +175°C Maximum power dissipation, P_D- - - - 200 mW Lead temperature (soldering, 10 seconds)- - - - - - - - - - - - +300°C Thermal resistance, junction-to-case (θ_JC): - - - - - - - - - - - - - - (see MIL-M-38510, appendix C) Junction temperature (T_J)- - - - - - +175°C

Supply voltage (V_DD - V_SS): Device types 01-06 - - - - - - - - 4.5 V dc to 12.5 V dc Device types 51-56 - - - - - - - - 4.5 V dc to 15 V dc Input low (V_IL) voltage range: Device types 01-06 - - - - - - - - 0-0.85 V dc at V_DD = 5 V dc, 0-2.1 V dc at V_DD = 12.5 V dc Device types 51-56 - - - - - - - - 0-1.5 V dc at V_DD = 5 V dc, 0-2.0 V dc at V_DD = 10 V dc, 0-4.0 V dc at V_DD = 15 V dc, V_OL = 10% V_DD, V_OH = 90% V_DD Input high (V_IH) voltage range: Device types 01-06 - - - - - - - - 3.95-5.0 V dc at V_DD = 5 V dc, 10.0-12.5 V dc at V_DD = 12.5 V dc Device types 51-56 - - - - - - - - 3.5-5.0 V dc at V_DD = 5 V dc, 8.0-10.0 V dc at V_DD = 10 V dc, 11.0-15.0 V dc at V_DD = 15 V dc, V_OL = 10% V_DD, V_OH = 90% V_DD Load capacitance- - - - - - - - - - - 50 pF maximum Operating temperature range - - - - - −55°C to +125°C

intended Use:

Microcircuits conforming to this specification are intended for original equipment design applications and logistic support of existing equipment.