JEDEC JESD 235
High Bandwidth Memory DRAM (HBM1, HBM2)
inactive
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| Organization: | JEDEC |
| Publication Date: | 1 November 2018 |
| Status: | inactive |
| Page Count: | 207 |
scope:
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 128 bit data bus operating at double data rate (DDR).
Document History
February 1, 2021
High Bandwidth Memory DRAM (HBM1, HBM2)
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another....
January 1, 2020
High Bandwidth Memory DRAM (HBM1, HBM2)
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another....
JEDEC JESD 235
November 1, 2018
High Bandwidth Memory DRAM (HBM1, HBM2)
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another....
November 1, 2015
High Bandwidth Memory (HBM) DRAM
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another....
October 1, 2013
High Bandwidth Memory (HBM) DRAM
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another....