JEDEC - JEP162A.01
System Level ESD Part II: Implementation of Effective ESD Robust Designs
active, Most Current
| Organization: | JEDEC |
| Publication Date: | 1 January 2021 |
| Status: | active |
| Page Count: | 140 |
scope:
This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2 system-level ESD stressing. These include both hard and soft failures, but more emphasis is placed on soft failures from all the observed and anticipated failures and failure scenarios. The methodology is a consistent characterization approach which applies to both IC interfaces and discrete PCB components.
Document History
JEP162A.01
January 1, 2021
System Level ESD Part II: Implementation of Effective ESD Robust Designs
This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2...
January 1, 2013
System Level ESD Part II: Implementation of Effective ESD Robust Designs
This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2...