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IEEE - 1500

Testability Method for Embedded Core-based Integrated Circuits

active, Most Current
Organization: IEEE
Publication Date: 16 June 2022
Status: active
Page Count: 168
scope:

IEEE Std 1500 is a standard design-for-testability method for integrated circuits (ICs) containing embedded nonmergeable cores. This method is independent of the underlying functionality of the IC or its individual embedded cores. The method supports the necessary requirements for the test of such ICs, while allowing for ease of interoperability of cores that might have originated from different sources. This method is usable for all classes of digital cores, including hierarchical cores.

Purpose

The aim of IEEE Std 1500 is to provide a consistent scalable solution to the test reuse challenges specific to the reuse of nonmergeable cores, while preserving the IP aspects that are often associated with these cores. This objective is achieved through provision of a core-centric methodology that enables successful integration of cores into SoCs.

Document History

1500
June 16, 2022
Testability Method for Embedded Core-based Integrated Circuits
IEEE Std 1500 is a standard design-for-testability method for integrated circuits (ICs) containing embedded nonmergeable cores. This method is independent of the underlying functionality of the IC or...
March 20, 2005
Testability Method for Embedded Core-based Integrated Circuits
IEEE Std 1500 has developed a standard design-for-testability method for integrated circuits (ICs) containing embedded nonmergeable cores. This method is independent of the underlying functionality...
March 20, 2005
Testability Method for Embedded Core-based Integrated Circuits
Foreword IEEE Std 1500 is a scalable standard architecture for enabling test reuse and integration for embedded cores and associated circuitry. It foregoes addressing analog circuits and focuses on...

References

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