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IEEE 1450.6

Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL)

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Organization: IEEE
Publication Date: 17 November 2005
Status: active
Page Count: 123
scope:

Unless the logic inside embedded cores can be merged with the surrounding user-defined logic (UDL), the SoC test requires reuse of test data and test structures specific to individual cores (designs) when integrated into larger systems. This standard defines language constructs sufficient to represent the context of a core and of the integration of that core into a system, to facilitate reuse of test data previously developed for that core. The SoC test also requires that the core be embedded in the SoC to allow for efficient testing of the logic external to the core. To that effect, this standard defines constructs that represent the test structures internal to the core for reuse in the creation of the tests for the logic outside the core. This provides constructs that will allow for the wrapping operation of an unwrapped core and the necessary wrapper specific information for a wrapped core. In particular, CTL shall support IEEE Std 1500-2005 for the information needs for wrapped and unwrapped cores. Semantic rules will be defined for the language to facilitate interoperability between the different entities (the core provider, the system integrator, and the automation tools) involved in the creation of an SoC. This standard is limited to SoC testing with multiple and/or hierarchical cores through digital interfaces.

All constructs defined in the CTL shall be consistent with IEEE Std 1450-1999 and extensions (STIL) to support the complete description of the test for cores integrated into SoC environments. Although the preferred syntax for the bulk of the test data is STIL, this language provides constructs for linking other test data representations to incorporate legacy cores. The constructs in the language shall support a vast variety of cores and different test methodologies with particular support for the IEEE 1500 standard for embedded core testing. These constructs shall facilitate the transportation of test information from the core provider to the system integrator and support test automation by providing a consistent and uniform definition of the constructs such that the information provided by a core provider is understood in the same way by the system integrator and the tools developed by EDA.

Purpose

To develop a language that will provide a sufficient description of a core to support reuse of test data developed for that core after integration into SoC environments, and to enable the creation of test patterns for the logic on the SoC external to the core.

Document History

IEEE 1450.6
November 17, 2005
Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL)
Unless the logic inside embedded cores can be merged with the surrounding user-defined logic (UDL), the SoC test requires reuse of test data and test structures specific to individual cores (designs)...
November 17, 2005
IEEE Standard Test Interface Language (STIL) for Digital Test Vector DataCore Test Language (CTL)
Unless the logic inside embedded cores can be merged with the surrounding user-defined logic (UDL), the SoC test requires reuse of test data and test structures specific to individual cores (designs)...

References

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