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IEEE 1450.1

IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450™1999) for Semiconductor Design Environments

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Organization: IEEE
Publication Date: 9 June 2005
Status: active
Page Count: 126
scope:

Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test (BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution of pattern constructs.

Structures are defined in STIL to support the definition of test patterns for sub-blocks of a design4 (i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test.

Structures are defined in STIL to relate fail information from device testing environments back to original stimulus and design data elements.

4Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O.

Document History

IEEE 1450.1
June 9, 2005
Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Semiconductor Design Environments
Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self...
IEEE 1450.1
June 9, 2005
IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450™1999) for Semiconductor Design Environments
Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self...
IEEE 1450.1
June 9, 2005
IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450™1999) for Semiconductor Design Environments
A description is not available for this item.

References

This document references:
IEEE 1364 - Standard Verilog Hardware Description Language
Published by IEEE on January 1, 2005
Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously...
This document references:
IEEE 1450 - Standard Test Interface Language (STIL) for Digital Test Vector Data
Published by IEEE on November 1, 2007
This standard defines a test description language that: a) Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment (ATE) environments;...
This document references:
IEEE 1450.6 - Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL)
Published by IEEE on November 17, 2005
Unless the logic inside embedded cores can be merged with the surrounding user-defined logic (UDL), the SoC test requires reuse of test data and test structures specific to individual cores (designs)...
This document references:
IEEE 1500 - Testability Method for Embedded Core-based Integrated Circuits
Published by IEEE on March 20, 2005
Foreword IEEE Std 1500 is a scalable standard architecture for enabling test reuse and integration for embedded cores and associated circuitry. It foregoes addressing analog circuits and focuses on...
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