IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450™1999) for Semiconductor Design Environments
|Publication Date:||9 June 2005|
Structures are defined in STIL to support usage as semiconductor simulation stimulus, including (1) mapping signal names to equivalent design references, (2) interface between scan and built-in self test (BIST) and the logic simulation, (3) data types to represent unresolved states in a pattern, (4) parallel or asynchronous pattern execution on different design blocks, and (5) expression-based conditional execution of pattern constructs.
Structures are defined in STIL to support the definition of test patterns for sub-blocks of a design4 (i.e., embedded cores) such that these tests can be incorporated into a complete higher level device test.
Structures are defined in STIL to relate fail information from device testing environments back to original stimulus and design data elements.
4Syntax in this document that is used in the definition of patterns for sub-blocks is summarized in Annex O.