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IEEE 1364

Standard Verilog Hardware Description Language

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Organization: IEEE
Publication Date: 1 January 2005
Status: active
Page Count: 590
scope:

Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.

The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:

 - The formal syntax and semantics of all Verilog HDL constructs

 - The formal syntax and semantics of standard delay format (SDF) constructs

 - Simulation system tasks and functions, such as text output display commands

 - Compiler directives, such as text substitution macros and simulation time scaling

 - The programming language interface (PLI) binding mechanism

 - The formal syntax and semantics of the Verilog procedural interface (VPI)

 - Informative usage examples

 - Informative delay model for SDF

 - The VPI header file

Document History

IEEE 1364
January 1, 2005
Standard Verilog Hardware Description Language
Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously...
November 26, 2003
Errata to Verilog Hardware Description Language - Correction Sheet
A description is not available for this item.
March 17, 2001
Standard Verilog Hardware Description Language
A description is not available for this item.
January 1, 1995
Standard Hardware Description Language Based on the Verilog Hardware Description Language
A description is not available for this item.

References

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