scope:

This specification covers the detail requirements for monolithic silicon, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510.

The device type shall be as follows:

Device type Circuit 01 Quadruple 2-Input NAND gate 02 Dual 4-Input NAND gate 03 Triple 3-input NAND gate 51 Quadruple 2-input NAND gate 52 Dual 4-input NAND gate 53 Triple 3-Input NAND gate

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated·as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) A F-1 (14-lead, ¼" × ¼"), flat package C D-1 (14-lead, ¼" × ¼"), dual-in-line package D F-2 (14-lead, ¼" × ⅜"), flat package X F-1 (14-lead, ¼" × ¼"), flat package, except A dimension = 0.1" (2.54 mm) maximum Y F-2 (14-lead, ¼" × ⅜"), flat package, except A dimension = 0.1" (2.54 mm) maximum

NOTES:

1. As an exception to 3.5.6.2.3 of MIL-M-38510, for case outlines X and Y only, the leads of bottom brazed ceramic packages (i.e., configuration 2 of case outlines F-1 or F-2) may have electroless nickel undercoating which shall be 50 to 200 microinches (1.2.7 to 5:08 µm) thick provided the lead finish is hot solder dip (i.e., finish letter A) and provided that, after any lead forming, an additional hot solder dip coating is applied which shall extend from the outer tip of the lead to no more than 0.015 inch (0.38 mm) from the package edge.

2. For bottom or side brazed packages, case outlines X and Y only, the S₁ dimension may go to .000 inch (.00 mm) minimum. Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: National Aeronautics and Space Administration, George C. Marshall Space Flight Center, ATTN: EGO2 Marshall Space Flight Center, Alabama 35812, using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Supply voltage range (V_DD-V_SS): Device types 01, 02, and 03 - - - - - - - - - - - - - - −0.5 V to +15.5 V Device types 51, 52, and 53 - - - - - - - - - - - - - - −0.5 V to +18 V Input current (each input) - - - - - - - - - - - - - - - - ±10 mA Input voltage range - - - - - - - - - - - - - - - - - - - (V_SS−0.5 V) ≤ V_I ≤ (V_DD + 0.5 V) Storage temperature range - - - - - - - - - - - - - - - - −65°C to +175°C Maximum power dissipation (P_D) - - - - - - - - - - - - - 200 mW Lead temperature (soldering, 10 seconds) - - - - - - - - - +300°C Thermal resistance, Junction-to-case - - - - - - - - - - - (See MIL-M-38510, appendix C) Junction temperature (T_J) - - - - - - - - - - - - - - +175°C

Device types 01, 02, and 03: Supply voltage (V_DD-V_SS) - - - - - - - - - - - - - - - 4.5 V dc to 12.5 V dc Input low voltage range (V_IL) - - - - - - - - - - - - 0-0.85 V dc @ V_DD = 5 V; 0-2.0 V dc @ V_DD = 10 V 0-2.1 V dc @ V_DD = 12.5 V Input high voltage range (V_IH) - - - - - - - - - - - - - 3.95-5.0 V dc @ V_DD = 5 V; 8-10 V dc @ V_DD = 10 V; 10.0-12.5 V dc @ V_DD = 12.5 V Device types 51, 52, and 53: Supply voltage (V_DD-V_SS) - - - - - - - - - - - - - - 4.5 V dc to 15 V dc Input low voltage range (V_IL) - - - - - - - - - - - - 0-1.5 V dc @ V_DD = 5 V dc, V_OL = 10% V_DD, V_OH = 90% V_DD, 0-2.0 V dc @ V_DD = 10 V dc. 0-4.0 V dc @ V_DD 15 V dc. Input high voltage range (V_IH) - - - - - - - - - - - - 3.5-5.0 V dc @ V_DD = 5 V dc, V_OL = 10% V_DD, V_OH = 90% V_DD, 8-10 V dc @ V_DD = 10 V dc 11.0-15.0 V dc @ V_DD = 15 V dc Ambient operating temperature (T_A) - - - - - - - - - - - −55°C to +125°C Load capacitance - - - - - - - - - - - - - - - - - - - - 50 pF maximum

intended Use:

Microcircuits conforming to this specification are intended for original equipment design applications and logisitic support of existing equipment.