scope:

This drawing describes device requirements for class 8 microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with .compliant non-JAN devices".

The complete PIN shall be as shown in the following example:

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function Gain error 01 LTC1090 10-bit data acquisition system ±2.0 LSB 02 LTC1290B 12-bit data acquisition system ±0.5 LSB 03 LTC1290C 12-bit data acquisition system ±1.0 LSB 04 LTC1290D 12-bit data acquisition system ±4.0 LSB

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style R GDIPl-T20 or CDIP2-T20 20 dual-in-line

The Lead finish shall be as specified in MIL-M-38510. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

Supply voltage (V+) to GND or (V−) - - - - - - - - - - 12 V dc Negative supply voltage (V−) - - - - - - - - - - - - - −6 V to GND Analog and reference input voltage range - - - - - - - (V−) −0.3 V to V+ +0.3 V Digital input voltage range - - - - - - - - - - - - - - −0.3 V to 12 V Digital output voltage range - - - - - - - - - - - - - −0.3 V to V+ +0.3 V Power dissipation (P_D) - - - - - - - - - - - - - - - - 500 mW Lead temperature (soldering, 10 seconds) - - - - - - - +300°C Storage temperature range - - - - - - - - - - - - - - - −65°C to +150°C Junction temperature (T_J) - - - - - - - - - - - - - - - 175°C Thermal resistance, junction-to-case (θ_JC) - - - - - - See MIL-STD-1835 Thermal resistance, junction-to-ambient (θ_JA) - - - - 70°C/W

Positive supply voltage range (V+) - - - - - - - - - - 4.5 v dc to 10 v dc Negative supply voltage range (V−) - - - - - - - - - - −5.5 V dc to 0 Shift clock frequency range (f_SCLK): Device type 01 - - - - - - - - - - - - - - - - - - - 0 to 1.0 MHz Device type 02, 03, 04 - - - - - - - - - - - - - - - 0 to 2.0 MHz A/D clock frequency range (f_ACLK): Device type 01 - - - - - - - - - - - - - - - - - - - f_SCLK to 2.0 MHz Device type 02, 03, 04 - - - - - - - - - - - - - - - f_SCLK to 4.0 MHz Total cycle time (t_CYC): Device type 01 - - - - - - - - - - - - - - - - - - - 10 SCLK + 48 ACLK cycles minimum Device type 02, 03, 04 - - - - - - - - - - - - - - - 12 SCLK + 56 ACLK cycles minimum Hold time, CS low after last SCLK negative edge (t_HCS) 0 ns minimum Hold time D_IN after SCLK positive edge (t_HD): Device type 01 - - - - - - - - - - - - - - - - - - - 150 ns minimum Device type 02, 03, 04 - - - - - - - - - - - - - - - 50 ns minimum Setup time CS negative edge before clocking in first address bit (t_SUCS): Device type 01 - - - - - - - - - - - - - - - - - - - 2 ACLK cycles + 1 μs minimum Device type 02, 03, 04 - - - - - - - - - - - - - - - 2 ACLK cycles + 100 ns minimum Setup time D_IN stable before SCLK positive edge (t_SUD): Device type 01 - - - - - - - - - - - - - - - - - - - 400 ns minimum Device type 02, 03, 04 - - - - - - - - - - - - - - - 50 ns minimum ACLK high time (t_WHACLK) - - - - - - - - - - - - - - - 127 ns minimum ACLK low time (t_WLACLK) - - - - - - - - - - - - - - - - 200 ns minimum [C bar][S bar] high time during conversion (t_WHCS): Device type 01 - - - - - - - - - - - - - - - - - - - 44 ACLK cycles minimum Device type 02, 03, 04 - - - - - - - - - - - - - - - 52 ACLK cycles minimum Ambient operating temperature range (T_A) - - - - - - - −55°C to +125°C

intended Use: