scope:

This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes B, Q, and M) and space application (device classes S and V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN shall be as shown in the following example:

Device classes M, B, and S RHA marked devices shall meet the MIL-M-38510 specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function 01 100336 4-stage counter/shift register

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 B or S Certification and qualification to MIL-M-38510 Q or V Certification and qualification to MIL-I-38535

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X GDIP5-T24 or CDIP6-T24 24 dual-in-line Y See figure 1 24 quad flat pack

The lead finish shall be as specified in MIL-M-38510 for classes M, B, and S or MIL-I-38535 for classes Q and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

Negative supply voltage range (V_EE) - - - - - - - - - - - - - −7.0 V dc to +0.5 V dc DC input voltage range (V_IN) - - - - - - - - - - - - - - - - - V_EE to +0.5 V Maximum dc output current (I_OUT) - - - - - - - - - - - - - - - −50 mA Storage temperature range - - - - - - - - - - - - - - - - - - −65°C to +150°C Lead temperature (soldering, 10 seconds) - - - - - - - - - - - +300°C Junction temperature (T_J) - - - - - - - - - - - - - - - - - - +175°C Maximum power dissipation (P_D) - - - - - - - - - - - - - - - - 1280 mW Thermal resistance, junction-to-case (θ_JC): Case X - - - - - - - - - - - - - - - - - - - - - - - - - - - See MIL-STD-1835 Case Y - - - - - - - - - - - - - - - - - - - - - - - - - - - 28°C/W

Negative supply voltage range (V_EE) - - - - - - - - - - - - - −5.7 V dc minimum to −4.2 V dc maximum High level input voltage range (V_IH) - - - - - - - - - - - - - −1.165 V dc minimum to −0.870 V dc maximum Low level input voltage range (V_IL) - - - - - - - - - - - - - −1.830 V dc minimum to −1.475 V dc maximum Case operating temperature range (T_C) - - - - - - - - - - - - −55°C to +125°C Minimum setup time, D₃ to CP (t_s) - - - - - - - - - - - - - - 1.4 ns Minimum hold time, D₃ to CP (t_h) - - - - - - - - - - - - - - - 0.9 ns Minimum setup time, P_n to CP (t_s) - - - - - - - - - - - - - - 1.7 ns Minimum hold time, P_n to CP (t_h) - - - - - - - - - - - - - - - 1.0 ns Minimum setup time, D_O/[C bar][E bar][T bar] to CP (t_s) - - - - - - - - - - - - 1.8 ns Minimum hold time, D_O/[C bar][E bar][T bar] to CP (t_h) - - - - - - - - - - - - - 0.7 ns Minimum setup time, [C bar][E bar][P bar] to CP (t_s) - - - - - - - - - - - - - - 1.8 ns Minimum hold time, [C bar][E bar][P bar] to CP (t_h) - - - - - - - - - - - - - - 0.6 ns Minimum setup time, S_n to CP (t_s) - - - - - - - - - - - - - - 3.3 ns Minimum hold time, S_n to CP (t_h) - - - - - - - - - - - - - - - 0.0 ns Minimum setup time, MR to CP (t_s) - - - - - - - - - - - - - - 2.6 ns Minimum pulse width, CP (t_w) - - - - - - - - - - - - - - - - - 1.6 ns Minimum pulse width, MR (t_w) - - - - - - - - - - - - - - - - - 2.0 ns Maximum clock frequency, CP (f_MAX) - - - - - - - - - - - - - - 325 MHz

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) - - - - - - - - XX percent 2/

intended Use: