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DLA - SMD-5962-95611

MICROCIRCUIT, MEMORY, DIGITAL CMOS, PROGRAMMABLE LOGIC CELL ARRAY, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 12 March 1996
Status: inactive
Page Count: 26
scope:

This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

The PIN is be as shown in the following example:

Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device types Generic number Circuit function Toggle Speed 01 3190A-05 16×20 9000 gate programmable array 4.1 ns 02 3190A-04 16×20 9000 gate programmable array 3.3 ns

The device class designator is a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535

The case outline(s) are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X CMGA8-175 175 1/ Pin grid array package Y See figure 1 164 Quad flat package Z See figure 1 164 Quad flat package

The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M.

Supply voltage range to ground potential (VCC) - - - - - −0.5 V dc to +7.0 V dc DC input voltage range - - - - - - - - - - - - - - - - - −0.5 V dc to VCC +0.5 V dc Voltage applied to three-state output(VTS) - - - - - - - −0.5 V dc to VCC +0.5 V dc Lead temperature (soldering, 10 seconds) - - - - - - - - +260°C Thermal resistance, junction-to-case (θJC): Case outline X - - - - - - - - - - - - - - - - - - - - See MIL-STD-1835 Case outlines Y, Z - - - - - - - - - - - - - - - - - - 20°C/W 3/ Junction temperature (TJ) - - - - - - - - - - - - - - - +150°C 4/ Storage temperature range - - - - - - - - - - - - - - - −65°C to +150°C

Case operating temperature Range(TC) - - - - - - - - - - −55°C to +125°C Supply voltage relative to ground(VCC) - - - - - - - - - +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) - - - - - - - - - - - - - - - - - - 0 V dc

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) - - - - - 6/ percent

intended Use:

Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.

Microcircuits... View More

Document History

March 24, 2014
MICROCIRCUIT, MEMORY, DIGITAL, CMOS 9000 GATE PROGRAMMABLE LOGIC ARRAY,MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
October 4, 1996
MICROCIRCUIT, MEMORY, DIGITAL CMOS, PROGRAMMABLE LOGIC CELL ARRAY, MONOLITHIC SILICON
A description is not available for this item.
SMD-5962-95611
March 12, 1996
MICROCIRCUIT, MEMORY, DIGITAL CMOS, PROGRAMMABLE LOGIC CELL ARRAY, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...

References

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