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JEDEC - JESD22-A105C

Power and Temperature Cycling

inactive
Organization: JEDEC
Publication Date: 1 January 2004
Status: inactive
Page Count: 12
scope:

The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases are periodically applied and removed. It is intended to simulate worst case conditions encountered in application environments. The power and temperature cycling test is considered destructive and is only intended for device qualification. This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures.

Document History

January 1, 2020
Power and Temperature Cycling
This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. The power and temperature cycling test is...
January 1, 2004
Power and Temperature Cycling
This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. The power and temperature cycling test is...
JESD22-A105C
January 1, 2004
Power and Temperature Cycling
The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases...
February 1, 1996
Test Method A105-B Power and Temperature Cycling
A description is not available for this item.
May 1, 1988
Test Method A105-A Power and Temperature Cycling
A description is not available for this item.
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