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DLA - SMD-5962-89551

MICROCIRCUITS, DIGITAL, HIGH SPEED CMOS, DUAL J-K POSITIVE EDGE-TRIGGERED FLIP-FLOP, MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 6 February 1989
Status: inactive
Page Count: 15
scope:

This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices".

The complete part number shall be as shown in the following example:

The device type shall identify the circuit function as follows:

Device type Generic number Circuit function 01 54AC109 Dual JK positive edge-triggered flip-flop

The case outlines shall be as designated in appendix C of MIL-M-38510 and as follows:

Outline letter Case outline E D-2 (16-lead, .840" × .310" × .200"), dual-in-line package F F-5 (16-lead, .440" × .285" × .085"), flat package 2 C-2 (20-terminal, .358" × .358" × .100"), square chip carrier package

Supply voltage range 1/ - - - - - - - - - - - - - - −0.5 V dc to+6.0 V dc DC input voltage range 1/ - - - - - - - - - - - - - −0.5 V dc to VCC+ 0.5 V dc DC output voltage range 1/ - - - - - - - - - - - - - −0.5 V dc to VCC+ 0.5 V dc Clamp diode current - - - - - - - - - - - - - - - - ±20 mA DC output current (per pin) - - - - - - - - - - - - ±50 mA DC VCC or GND current (per pin) - - - - - - - - - - ±100 mA Storage temperature range - - - - - - - - - - - - - −65°C to 150°C Maximum power dissipation (PD) - - - - - - - - - - - 500 mW Lead temperature (soldering, 10 seconds) - - - - - - +300°C Thermal resistance, junction-to-case (θJC) - - - - - See MIL-M-38510, appendix C Junction temperature (TJ) 2/ - - - - - - - - - - - +175°C

Supply voltage range (VCC) 1/ - - - - - - - - - - - 3.0 V dc to 5.5 V dc Input voltage range - - - - - - - - - - - - - - - - 0.0 V dc to VCC Output voltage range - - - - - - - - - - - - - - - - 0.0 V dc to VCC Case operating temperature range (TC)- - - - - - - - −55°C to +125°C Input rise or fall times: VCC = 3.6 V to 5.5 V - - - - - - - - - - - - - - - 0 to 8 ns/V Minimum setup time, Jn or Kn to CPn (ts): TC = +25°C, VCC = 3.0 V - - - - - - - - - - - 6.5 ns TC = +25°C, VCC = 4.5 V - - - - - - - - - - - 4.5 ns TC = −55°C to +125°C, VCC = 3.0 V - - - - 8.0 ns TC = −55°C to +125°C, VCC = 4.5 V - - - - 5.5 ns Minimum hold time, Jn or Kn to CPn (th): TC = +25°C, VCC = 3.0 V - - - - - - - - - - - 0.0 ns TC = +25°C, VCC = 4.5 V - - - - - - - - - - - 0.5 ns TC = −55°C to +125°C, VCC = 3.0 V - - - - 0.0 ns TC = −55°C to +125°C, VCC = 4.5 V - - - - 0.5 ns Minimum pulse width CPn (tw): TC = +25°C, VCC = 3.0 V - - - - - - - - - - - 5.0 ns TC = +25°C, VCC = 4.5 V - - - - - - - - - - - 5.0 ns TC = −55°C to +125°C, VCC = 3.0 V - - - - 5.5 ns TC = −55°C to +125°C, VCC = 4.5 V - - - - 5.0 ns Minimum pulse width [C bar][D bar]n or [S bar][D bar]n (tw): TC = +25°C, VCC = 3.0 V - - - - - - - - - - - 6.0 ns TC = +25°C, VCC = 4.5 V - - - - - - - - - - - 5.0 ns TC = −55°C to +125°C, VCC = 3.0 V - - - - 8.0 ns TC = −55°C to +125°C, VCC = 4.5 V - - - - 5.5 ns Minimum recovery time, [C bar][D bar]n, [S bar][D bar]n to CPn (trec): TC = +25°C, VCC = 3.0 V - - - - - - - - - - - 0.5 ns TC = +25°C, VCC = 4.5 V - - - - - - - - - - - 0.5 ns TC = −55°C to +125°C, VCC = 3.0 V - - - - 0.5 ns TC = −55°C to +125°C, VCC = 4.5 V - - - - 0.5 ns Maximum frequency, CPn (fmax): TC = +25°C, VCC = 3.0 V - - - - - - - - - - - 85 MHz TC = +25°C, VCC = 4.5 V - - - - - - - - - - - 95 MHz TC = −55°C to +125°C, VCC = 3.0 V - - - - 65 MHz TC = −55°C to +125°C, VCC = 4.5 V - - - - 95 MHz

intended Use:

Microcircuits conforming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the required function are not available for... View More

Document History

November 29, 2021
MICROCIRCUIT, DIGITAL, ADVANCED CMOS, DUAL J-K POSITIVE EDGE-TRIGGERED FLIP-FLOP, MONOLITHIC SILICON
Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead...
July 24, 2015
MICROCIRCUIT, DIGITAL, ADVANCED CMOS, DUAL J-K POSITIVE EDGE-TRIGGERED FLIPFLOP, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead finishes are...
May 1, 2009
MICROCIRCUIT, DIGITAL, ADVANCED CMOS, DUAL J-K POSITIVE EDGE-TRIGGERED FLIPFLOP, MONOLITHIC SILICON
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
July 27, 2001
MICROCIRCUITS, DIGITAL, HIGH SPEED CMOS, DUAL J-K POSITIVE EDGE-TRIGGERED FLIP-FLOP, MONOLITHIC SILICON
A description is not available for this item.
SMD-5962-89551
February 6, 1989
MICROCIRCUITS, DIGITAL, HIGH SPEED CMOS, DUAL J-K POSITIVE EDGE-TRIGGERED FLIP-FLOP, MONOLITHIC SILICON
This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices"....
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