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NPFC - MIL-M-38510/51

MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 30 April 1984
Status: inactive
Page Count: 67
scope:

This specification covers the detail requirements for monolithic silicon, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510.

The device type shall be as follows:

Device type Circuit 01 Dual D-type edge-triggered flip-flop 02 Dual J-K master slave flip-flop 03 Quad 3-state R/S latch 51 Dual D-type edge-triggered flip-flop 52 Dual J-K master slave flip-flop 53 Quad 3-state R/S latch

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) A F-1 (14-lead, ¼" × ¼"), flat package C D-1 (14-lead, ¼" × ¾"), dual-in-line package D F-2 (14-lead, ¼" × ⅜"), flat package E D-2 (16-lead, ¼" × ⅞"). dual-in-line package F F-5 (16-lead, ¼" × ⅜"), flat package X F-1 (14-lead, ¼" × ¼"), flat package, except A dimension = 0.1" (2.54 mm maximum) Y F-2 (14-lead, ¼" × ⅜"), flat package, except A dimension = 0.1" (2.54 mm maximum) Z F-5 (16-lead, ¼ × ⅜"), flat package, except A dimension = 0.1" (2.54 mm maximum)

NOTES:

1. As an exception to 3.5.6.2.3 of MIL-M-38510, for case outlines X, Y, and Z only, the leads of bottom brazed ceramic packages (i.e., configuration 2 of case outlines F-l, F-2, or F-5) may have electroless nickel undercoating which shall be 50 to 200 microinches (1.27 to 5.08 µm) thick provided the lead finish is hot solder dip (i.e., finish letter A) and provided that, after any lead forming, an additional hot solder dip coating is applied which shall extend from the outer tip of the lead to no more than 0.015 inch (0.38 mm) from the package edge.

2. For bottom or side braded packages, case outlines X, Y, and Z only, the S1 dimension may go to .000 inch (.00 mm) mimimum. Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: National Aeronautics and Space Administration, George C. Marshall Space Flight Center, ATTN: EG02, Marshall Space Flight Center, AL 35812, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Supply voltage range (VDD - VSS - - - - - - - - - - - - Device types 01, 02, and 03 - - - - - - - - - - - - - - −0.5 V to +15.5 V Device types 51, 52, and 53 - - - - - - - - - - - - - - −0.5 V to +18.0 V Input current (each input) - - - - - - - - - - - - - - - - ±10 mA Input voltage range - - - - - - - - - - - - - - - - - - - (VSS - 0.5 V) ≤ VI ≤ (VDD + 0.5 V) Storage temperature range - - - - - - - - - - - - - - - - −65°C to +175°C Maximum power dissipation (PD) - - - - - - - - - - 200 mW Lead temperature (soldering, 10 seconds)- - - 300°C Thermal resistance, junction-to-case (θJC):- (See MIL-M-38510, appendix C) Junction temperature (TJ) - - - - - - - - - - - - - 175°C

Device types 01, 02, and 03: Supply voltage (VDD - VSS) - - - - - - - - - - - - - - 4.5 V dc to 12.5 V dc Input low (VIL) voltage range - - - - - - - - - - - - - 0-0.85 V dc @ VDD = 5 V; 0-2.0 V dc @ VDD = 10 V 0-2.1V dc @ VDD =12.5 V Input high (VIH) voltage range - - - - - - - - - - - - 3.95-5.0 V dc @ VDD = 5 V; 8-10 V dc @ VDD = 10 V 10.0-12.5 V dc @ VDD = 12.5 V Device types 51, 52, and 53: Supply voltage (VDD - VSS - - - - - - - - - - - - - - - 4.5 V dc to 15 V dc Input low (VIL) voltage range - - - - - - - - - - - - - 0-1.5 V dc @ VDD = 5 V dc, VOL = 10% VDD, VOH = 90% VDD, 0-2.0 V dc @ 10 V dc, 0-4.0 V dc @ VDD = 15 V dc Input high (VIH) voltage range - - - - - - - - - - - - 3.5-5.0 V dc @ VDD = 5 V dc, VOL = 10% VDD, VOH = 90% VDD, 8.0-10.0 V dc @ VDD = 10 V dc, 11.0-15.0 V dc @ VDD = 15 V dc Load capacitance - - - - - - - - - - - - - - - - - - - - 50 pF maximum Ambient operating temperature range - - - - - - - - - - - −55°C to +125°C

intended Use:

Microcircuits conforming to this specification are intended for original equipment design applications and logistic support of existing equipment.

Document History

March 9, 2021
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July 20, 2011
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April 28, 1999
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October 6, 1995
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August 31, 1988
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November 15, 1984
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/51
April 30, 1984
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are...
September 30, 1982
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
A description is not available for this item.
November 10, 1981
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
A description is not available for this item.
January 22, 1980
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
A description is not available for this item.
November 27, 1978
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
A description is not available for this item.
October 13, 1978
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
A description is not available for this item.
February 10, 1978
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
A description is not available for this item.
September 10, 1976
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
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May 5, 1976
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
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October 10, 1975
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August 10, 1974
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A description is not available for this item.
January 21, 1974
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August 8, 1973
MICROCIRCUITS, DIGITAL, CMOS, FLIP-FLOPS AND LATCHES, MONOLITHIC SILICON
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January 12, 1973
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References

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