DLA - SMD-5962-94616
MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, SCAN TEST DEVICE WITH OCTAL BUS TRANSCEIVER AND REGISTER, THREE-SATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON
| Organization: | DLA |
| Publication Date: | 26 April 1994 |
| Status: | inactive |
| Page Count: | 26 |
scope:
This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
The PIN shall be as shown in the following example:
Device class M RHA marked devices shall meet the MIL-I-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-I-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
The device type(s) shall identify the circuit function as follows:
Device type Generic number Circuit function 01 54ABT8652 Scan test device with octal bus transceiver and register, three-state outputs, TTL compatible inputs
The device class designator shall be a single letter identifying the product assurance level as follows:
Device class Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualification to MIL-I-38535
The case outline(s) shall be as designated in MIL-STD-1835, and as follows:
Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 Dual-in-line 3 CQCC1-N28 28 Square chip carrier
The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-I-38535 for classes Q and V. Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.
Supply voltage range (VCC) - - - - - - - - - - - - - - - - - - - - - - - −0.5 V dc to +7.0 V dc DC input voltage range (I/O ports) (VIN) - - - - - - - - - - - - - - - - −0.5 V dc to +5.5 V dc 4/ DC input voltage range (except I/O ports) (VIN) - - - - - - - - - - - - −0.5 V dc to +7.0 v dc 4/ DC output voltage range (VOUT) - - - - - - - - - - - - - - - - - - - - - −0.5 v dc to +5.5 V dc 4/ DC output current (IOL) (per output) - - - - - - - - - - - - - - - - - - +96 mA DC input clamp current (IIK) (VIN < 0.0 V) - - - - - - - - - - - - - - - −18 mA DC output clamp current (IOK) (VOUT < 0.0 V) - - - - - - - - - - - - - - −50 mA Storage temperature range (TSTG) - - - - - - - - - - - - - - - - - - - - −65°C to +150°C Lead temperature (soldering, 10 seconds) - - - - - - - - - - - - - - - - +300°C Thermal resistance, junction-to-case (ΘJC) - - - - - - - - - - - - - - - See MIL-STD-1835 Junction temperature (TJ) - - - - - - - - - - - - - - - - - - - - - - - +175°C Maximum power dissipation (PD) - - - - - - - - - - - - - - - - - - - - - 420 mW 5/
Supply voltage range (VCC) - - - - - - - - - - - - - - - - - - - - - - - +4.5 V dc to +5.5 V dc Input voltage range (VIN) - - - - - - - - - - - - - - - - - - - - - - - +0.0 V dc to VCC Output voltage range (VOUT) - - - - - - - - - - - - - - - - - - - - - - +0.0 v dc to VCC Maximum low level input voltage (VIL) - - - - - - - - - - - - - - - - - 0.8 V Minimum high level input voltage (VIH) - - - - - - - - - - - - - - - - - 2.0 V Maximum high level output current (IOH) - - - - - - - - - - - - - - - - −24 mA Maximum low level output current (IOL) - - - - - - - - - - - - - - - - - +48 mA Maximum input rise or fall rate (Δt/ΔV) - - - - - - - - - - - - - - - - 10 ns/V Minimum setup time (ts): An before CLKAB↑ or Bn before CLKBA↑ - - - - - - - - - - - - - - - - - 5.1 ns An, Bn, CLKAB, CLKBA, SAS, SBA, OEAB, or [O bar][E bar][B bar][A bar] before TCK↑ - - - - - - 7.0 ns TDI before TCK↑ - - - - - - - - - - - - - - - - - - - - - - - - - - - 6.0 ns TMS before TCK↑ - - - - - - - - - - - - - - - - - - - - - - - - - - - 6.0 ns Minimum hold time (th): An after CLKAB↑ or Bn after CLKBA↑ - - - - - - - - - - - - - - - - - - 0.5 ns An, Bn, CLKAB, CLKBA, SAS, SBA, OEAB, or [O bar][E bar][B bar][A bar] after TCK↑ - - - - - - - 0.6 ns TDI after TCK↑ - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0.9 ns TMS after TCK↑ - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0.9 ns Minimum pulse width (tw): CLKAB or CLKBA high or low - - - - - - - - - - - - - - - - - - - - - - 3.0 ns TCK high or low - - - - - - - - - - - - - - - - - - - - - - - - - - - 5.0 ns Minimum delay time, power-up to TCK↑ (td) - - - - - - - - - - - - - - - 50.0 ns 6/ Minimum rise time, VCC power-up (ti) - - - - - - - - - - - - - - - - - - 1.0 µs 6 Maximum clock frequency (fCLK): CLKAB or CLKBA - - - - - - - - - - - - - - - - - - - - - - - - - - - - 100 MHz TCK - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50 MHz Case operating temperature range (TC) - - - - - - - - - - - - - - - - - −55°C to +125°C
Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) - - - - - - - - - - - - - XX percent 7/
intended Use:
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
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