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NPFC - MIL-M-38510/246

MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 246,144-BIT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 13 January 1987
Status: active
Page Count: 36
scope:

This specification covers the detail requirements for monolithic silicon, NMOS, 262,144/1-bit, dynamic random access memory. Two product assurance classes, two electrical performance categories, two refresh mode options, and two case styles are provided and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510 and as specified herein.

The device types shall be as shown in the following:

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) E D-2 (16-lead, 0,250" × 0.875"), dual-in-line package X (18-terminal, 0.285" × 0.495"), chip carrier (see figure 1)

Beneficial comments (recommendations, addition, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441, by using the self-addressed Standardization Document Improvement proposal (DD Form 1426) appearing at the end of this document or by letter.

Voltage on any pin relative to VSS - - - - - - - - - - −1.5 V to +7.0 V Storage temperature range (ambient) - - - - - - - - - −65°C to +150°C Power dissipation (minimum cycle time) - - - - - - - - 1.0 W Lead temperature (soldering, 5 seconds) - - - - - - - +270°C Junction temperature (TJ) 3/ - - - - - - - - - - - - - +150°C Short circuit output current - - - - - - - - - - - - - 50 mA Thermal resistance (minimum cycle time): Case E - - - - - - - - - - - - - - - - - - - - - - - See MIL-M-38510, appendix C Case X - - - - - - - - - - - - - - - - - - - - - - - θJC = 60°C/W 4/

The error rate shall not exceed 9.16 × 10−11 errors per bit-day at sea level, under the following test conditions:

a. VCC = 4.5 V.

b. TC = +25°C.

c. Data pattern = checkerboard.

d. Cycle time = 250 ns.

Supply voltage (VCC) - - - - - - - - - - - - - - - - - 4.5 V dc minimum to 5.5 V dc maximum Power supply and signal reference (VSS) 5/ - - - - - - 0.0 V dc High level input voltage: all inputs (VIH) - - - - - 2.4 V dc minimum to 6.5 V dc maximum Low level input voltage: all inputs (VIL) - - - - - - −1.5 V dc minimum to +0.8 V dc maximum Refresh cycle time (tRFSH) - - - - - - - - - - - - - - 2.0 ms Operating case temperature range (TC) - - - - - - - - −55°C to +110°C

intended Use:

Microcircuits conforming to this specification are intended for use for Government microcircuit applications (original equipment) and logisitic purposes.

Document History

August 17, 2020
Microcircuits, Memory, Digital, NMOS, 246,144-Bit Dynamic Random Access Memory (DRAM), Monolithic Silicon
A description is not available for this item.
November 9, 2010
MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 246,144-BIT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON
A description is not available for this item.
January 31, 2006
MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 246,144-BIT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON
A description is not available for this item.
April 26, 2001
MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 246,144-BIT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON
A description is not available for this item.
July 24, 1995
MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 246,144-BIT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON
A description is not available for this item.
June 25, 1987
MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 246,144-BIT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/246
January 13, 1987
MICROCIRCUITS, MEMORY, DIGITAL, NMOS, 246,144-BIT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, NMOS, 262,144/1-bit, dynamic random access memory. Two product assurance classes, two electrical performance categories, two...

References

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