NPFC - MIL-M-38510/336
MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, SHIFT REGISTERS, CASCADABLE, MONOLITHIC SILICON
| Organization: | NPFC |
| Publication Date: | 9 August 1983 |
| Status: | inactive |
| Page Count: | 16 |
scope:
This specification covers the detail requirements for monolithic silicon, advanced Schottky TTL, shift register microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the part number.
The part number shall be in accordance with MIL-M-38510, and as specified herein.
The device type shall be as follows:
Device type Circuit 01 4-bit bidirectional universal shift register
The device class shall be the product assurance level as defined in MIL-M-38510.
The case outline shall be designated as follows:
Letter Case outline (see MIL-M-38510, appendix C) E D-2 (16-lead, ¼" × ⅞") dual-in-line package F F-5 (16-lead, ¼" × ⅜") flat package X C-2 (20-terminal, .350" × .350") square chip carrier package
Supply voltage range - - - - - - - - - - - - - - −0.5 V to +7.0 V Input voltage range- - - - - - - - - - - - - - - −1.2 V at −18 mA to +7.0 V Storage temperature range- - - - - - - - - - - - −65°C to +150°C Maximum power dissipation per device (PD) 1/ - - 253 mW Lead temperature (soldering, 10 seconds) - - - - 300°C Thermal resistance, junction to case (θJC): Case E- - - - - - - - - - - - - - - - - - - - 50°C/W Cases F, and X - - - - - - - - - - - - - - - 70°C/W Junction temperature (TJ)- - - - - - - - - - - - 175°C
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.
Supply voltage - - - - - - - - - - - - - - - 4.5 V minimum to 5.5 V maximum Minimum high level input voltage (VIH) - - - 2.0 V Maximum low level input voltage (VIL)- - - - 0.8 V Width of clock pulse high tPW(CPH) - - - - - - - - - - - - - - - - - 6.0 ns minimum Width of master reset pulse low tPW(MRL) - - - - - - - - - - - - - - - - - 5.0 ns minimum Setup time data high to clock pulse tSD(H) - - - - - - - - - - - - - - - - - - 5.0 ns minimum Setup time data low to clock pulse tSD(L) - - - - - - - - - - - - - - - - - - 4.0 ns minimum Hold time data high to clock pulse tHD(H) - - - - - - - - - - - - - - - - - - 2.0 ns minimum Hold time data low to clock pulse tHD(L) - - - - - - - - - - - - - - - - - - 1.0 ns minimum Setup time select high to clock pulse tSS(H) - - - - - - - - - - - - - - - - - - 10.0 ns minimum Setup time select low to clock pulse tSS(L) - - - - - - - - - - - - - - - - - - 8.0 ns minimum Hold time select high to clock pulse tHS(H) - - - - - - - - - - - - - - - - - - 0.0 ns minimum Hold time select low to clock pulse tHS(L) - - - - - - - - - - - - - - - - - - 0.0 ns minimum Recovery time master reset to clock pulse trec([M bar][R bar]/CP)- - - - - - - - - - - - - - - - 9.0 ns minimum Input clock frequency f(clock) - - - - - - - 0 - 80 MHz Case operating temperature range (TC)- - - - −55°C to +125°C
intended Use:
Microcircuits conforming to this specification are intended for original equipment design applications and logistic support of existing equipment.
Document History
