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NPFC - MIL-M-38510/56

MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 19 February 1988
Status: inactive
Page Count: 62
scope:

This specification covers the detail requirements for monolithic silicon, CMOS counter/divider microcircuits. Two product assurance classes and a choice of case outline/lead finish are provided for each type and are reflected in the complete part number.

The complete part number shall be in accordance with MIL-M-38510.

The device type shall be as follows:

Device type Circuit 01 Decade counter/divider 02 Presettable divide-by-"N" counter 03 14-stage ripple-carry binary counter/divider 04 Divide-by-8 counter/divider 05 7-stage binary counter 51 Decade counter/divider 52 Presettable divide-by-"N" counter 53 14-stage ripple-carry binary counter/divider 54 Divide-by-8 counter/divider 55 7-stage binary counter

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated as follows:

Letter Case outline, MIL-M-38510, appendix C A F-1 (14-lead, ¼" × ¼"), flat-package B F-3 (14-lead, 3/16" × ¼"), flat-package C D-1 (14-lead, ¼" × ¾"), dual-in-line package D F-2 (14-lead, ¼" × ⅜"), flat-package E D-2 (16-lead, ¼" × ⅞"), dual-in-line package F F-5 (16-lead, ¼" × ⅜"), flat-package N F-5A (16-lead, ¼" × ⅜"), flat package T F-2A (14-lead, ¼" × ⅜"), flat package X F-1 (14-lead, ¼" × ¼"), flat-package except dimension "A" = 0.1 (2.54 mm), maximum Y F-2 (14-lead, ¼" × ⅜"), flat-package except dimension "A" = 0.1 (2.54 mm), maximum Z F-5 (16-lead, ¼" × ⅜"), flat-package except dimension "A" = 0.1 (2.54 mm), maximum

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: NASA Parts Project Office, Code 311.A, NASA/Goddard Space Flight Center, Greenbelt, Md 20771 by using the self-addressed Standardization Document Improvement (DD Form 1426) Proposal appearing at the end of this document or by letter.

NOTES

1. As an exception to nickel plate or undercoating paragraph of MIL-M-38510, for class outlines X, Y, and Z only, the leads of bottom brazed ceramic packages (i.e. configuration 2 of case outline F-l, F-2, or F-5) may have electroless nickel undercoating which shall be 50 to 200 microinches (1.27 to 5.08 µm) thick provided the lead finish is hot solder dip (i.e. finish letter A) and provided that, after any lead forming, an additional hot solder dip coating is applied which shall extend from the outer tip of the lead to no more than 0.015 inch (0.38 mm) from the package edge.

2. For bottom or side brazed packages, case outlines X, Y, and Z only, the S1 dimension may go to .000 inch (.00 mm) minimum.

Supply voltage range (VDD − VSS): Device types 01, 02, 03, 04, and 05 - - - - −0.5 to +15.5 V dc Device types 51, 52, 53, 54, and 55 - - - - −0.5 to +18 V dc Input current (each input)- - - - - - - - - - ±10 mA Input voltage range - - - - - - - - - - - - - (VSS −0.5 V dc) ≤ VI ≤ (VDD +0.5 V dc) Storage temperature range - - - - - - - - - - −65°C to +175°C Maximum power dissipation, (PD) - - - - - - - +200 mW Lead temperature (soldering 10 seconds) - - - +300°C Thermal resistance, junction to case (θJC)- - (See MIL-M-38510, appendix C) Junction temperature (TJ) - - - - - - - - - - +175°C

Supply voltage range (VCC or VDD - VSS): Device types 01, 02, 03, 04, and 05- - - - 4.5 to 12.5 V dc Device types 51, 52, 53, 54, and 55- - - - 4.5 to 15.0 V dc Input low (VIL) voltage range: Device types 01, 02, 03, 04, and 05- - - - 0 to 0.85 V dc @ VDD = 5 V dc 0 to 2.0 V dc @ VDD = 10 V dc 0 to 2.1 V dc @ VDD = 12.5 V dc Device types 51, 52, 53, 54, and 55- - - - 0 to 1.5 V dc @ VDD = 5 V dc VOL = 10% VDD VOH = 90% VDD 0 to 2.0 V dc at VDD = 10 V dc 0 to 4.0 V dc @ VDD = 15 V dc Input high (VIH) voltage range: Device types 01, 02, 03, 04, and 05- - - - 3.95 to 5.0 V dc @ VDD = 5 V dc 8 to 10 V dc @ VDD = 10 V dc 10.0 to 12.5 V dc @ VDD = 12.5 V dc Device types 51, 52, 53, 54, and 55- - - - 3.5 to 5.0 V dc @ VDD = 5 V dc VOL = 10% VDD VOH = 90% VDD 8 to 10.0 V dc @ VDD = 10 V dc 11.0 to 15.0 V dc @ VDD = 15 V dc Ambient operating temperature range (TA) - - −55°C to 125°C Load capacitance - - - - - - - - - - - - - - 50 pF maximum

intended Use:

Microcircuits conforming to this specification are intended for original equipment design applications and logistic support of existing equipment.

Document History

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MIL-M-38510/56
February 19, 1988
MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, CMOS counter/divider microcircuits. Two product assurance classes and a choice of case outline/lead finish are provided for...
April 30, 1984
MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON
A description is not available for this item.
October 25, 1983
MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON
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September 30, 1982
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December 2, 1981
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August 20, 1981
MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON
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April 23, 1979
MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON
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November 7, 1978
MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON
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April 28, 1978
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November 22, 1977
MICROCIRCUITS, DIGITAL, CMOS, COUNTERS/DIVIDERS, MONOLITHIC SILICON
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December 27, 1976
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May 5, 1976
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July 10, 1974
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August 8, 1973
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References

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