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NPFC - MIL-M-38510/171

MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC

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Organization: NPFC
Publication Date: 30 April 1984
Status: inactive
Page Count: 45
scope:

This specification covers the detail requirements for monolithic silicon, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510.

The device type shall be as follows:

Device type Circuit 01 Quad 2-input OR gate 02 Dual 4-input OR gate 03 Triple 3-input OR gate

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outline shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) A F-1 (14-lead, ¼" × ¼"), flat package C D-1 (14-lead, ¼" × ¾"), dual-in-line package D F-2 (14-lead, ¼" × ⅜"), flat package X F-1 (14-lead, ¼" × ¼"), flat package, except A dimension = 0.1" (2.54 mm max) Y F-2 (14-lead, ¼" × ⅜"), flat package, except A dimension = 0.1" (2.54 mm max)

NOTES:

1. As an exception to 3.5.6.2.3 of MIL-M-38510, for case outlines X and Y only, the leads of bottom brazed ceramic packages (i.e., configuration 2 of case outlines F-1 or F-2) may have electroless nickel undercoating which shall be 50 to 200 microinches (1.27 to 5.08 µm) thick provided the lead finish is hot solder dip (i.e., finish letter A) and provided that, after any lead forming, an additional hot solder dip coating is applied which shall extend from the outer tip of the lead to no more than 0.015 inch (0.38 mm) from the package edge.

2. For bottom or side braded packages, case outlines X and Y only, the S1 dimension may go to .000 inch (.00 mm) minimum. Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: George C. Marshall Space Flight Center, National Aeronautics and Space Administration, ATTN: EGO2, Marshall Space Flight Center, AL 35812 by using the self addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Supply voltage range (VDD-VSS) - - - - - - - - - - −0.5 V to +18 V Input current (each input) - - - - - - - - - - - - ±10 mA Input voltage range - - - - - - - - - - - - - - - (VSS −0.5) ≤ VI ≤ (VDD + 0.5) Storage temperature range - - - - - - - - - - - - −65°C to +175°C Maximum power dissipation (PD) - - - - - - - - - - 200 mW Lead temperature (soldering, 10 seconds) - - - - - +300°C Thermal resistance, junction-to-case (θJC): - (See MIL-M-38510, appendix C) Junction temperature (TJ) - - - - - - - - - - +175°C

Supply voltage range (VDD-VSS) - - - - - - - - - - 4.5 V to 15 V Input low voltage range (VIL)- - - - - - - - - - - 0 to 1.5 Vdc at VDD = 5 Vdc, VOL = 10% VDD, VOH = 90% VDD 0 to 2.0 Vdc @ VDD = 10 Vdc, 0 to 4.0 Vdc @ VDD = 15 Vdc Input high voltage range (VIH) - - - - - - - - - - 3.5 to 5.0 Vdc at VDD = 5 Vdc, VOL = 10% VDD, VOH = 90% VDD, 8.0 to 10.0 Vdc @ VDD = 10 Vdc, 11.0 to 15.0 Vdc @ VDD = 15 Vdc Ambient operating temperature range (TA) - - - - - −55°C to +125°C

intended Use:

Microcircuits conforming to this specification are intended for original equipment design applications and logistic support of existing equipment.

Document History

Microcircuits, Digital, CMOS, or Gates, Monolithic Silicon, Positive Logic
A description is not available for this item.
June 20, 2018
Microcircuits, Digital, CMOS, or Gates, Monolithic Silicon, Positive Logic
A description is not available for this item.
September 9, 2013
Microcircuits, Digital, CMOS, or Gates, Monolithic Silicon, Positive Logic
A description is not available for this item.
December 5, 2008
Microcircuits, Digital, CMOS, or Gates, Monolithic Silicon, Positive Logic
This specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness...
February 17, 2004
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
This specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness...
April 23, 1999
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
August 9, 1996
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
October 4, 1988
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
MIL-M-38510/171
April 30, 1984
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
This specification covers the detail requirements for monolithic silicon, CMOS logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are...
September 20, 1982
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
November 10, 1981
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
June 16, 1980
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
July 30, 1979
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
February 23, 1979
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
October 23, 1978
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.
July 14, 1978
MICROCIRCUITS, DIGITAL, CMOS, OR GATES, MONOLITHIC SILICON, POSITIVE LOGIC
A description is not available for this item.

References

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