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NPFC - MIL-M-38510/655

MICROCIRCUITS, DIGITAL, HIGH-SPEED CMOS, BUS TRANSCEIVERS WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON

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Organization: NPFC
Publication Date: 30 September 1986
Status: inactive
Page Count: 82
scope:

This specification covers the detail requirements for monolithic silicon, high speed, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number.

The part number shall be in accordance with MIL-M-38510, and as specified herein.

The device types shall be as follows:

Device type Circuit 01 Quadruple inverting bus transceivers with three-state outputs 02 Quadruple non-inverting bus transceivers with three-state outputs 03 Octal non-inverting bus transceivers with three-state outputs 04, 05 To be included later 06 Octal inverting bus transceivers with three-state outputs 07 Octal non-inverting or inverting bus transceivers with three-state outputs 08 Octal non-inverting bus transceivers with three-state outputs 09 Octal inverting bus transceivers with three-state outputs 53 Octal non-inverting bus transceivers with three-state outputs and TTL-input voltage compatibility

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outlines shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) C D-1 (14-lead, ¼" × ¾"), dual-in-line package L D-9 (24-lead, ¼" × 1 ¼"), dual-in-line package R D-8 (20-lead, ¼" × 1 1/16"), dual-in-line package 2 C-2 (20-terminal, .350" × .350") square chip carrier package 3 C-4 (28-terminal, .450" × .450"), square chip carrier package

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) ,appearing at the end of this document or by letter.

Supply voltage (VCC)- - - - - - - - - - - - - −0.5 V dc +7.0 V dc DC input voltage (VIN)- - - - - - - - - - - - −0.5 V dc to VCC +0.5 V dc DC output voltage (VOUT)- - - - - - - - - - - −0.5 V dc to VCC +0.5 V dc Clamp diode current (IIK, IOK)- - - - - - - - ±20 mA DC output current per pin (IOUT)- - - - - - - ±35 mA DC VCC or GND current per pin (IOC) - - - - - ±70 mA Storage temperature range (TSTG)- - - - - - - −65°C to +150°C Maximum power dissipation (PD)- - - - - - - - 300 mW Lead temperature (soldering, 10 seconds)- - - +300°C Thermal resistance, Junction-to-case (OJC): Cases C, L, and R - - - - - - - - - - - - - (See MIL-M-38510, appendix C) Case 2- - - - - - - - - - - - - - - - - - - 60°C/W Case 3- - - - - - - - - - - - - - - - - - - TBD Junction temperature (TJ) - - - - - - - - - +175°C

Device types 01, 02, 03, 06, 07, 08, 09: Input low (VIL) maximum voltage - - - - - - - 0.3 V at VCC = 2 V 0.9 V at VCC = 4.5 V 1.2 V at VCC = 6 V Input high (VIH) minimum voltage- - - - - - - 1.5 V at VCC = 3 V 3.15 V at VCC = 4.5 V 4.2 V at VCC = 6 V Operating ambient temperature range TA- - - - - −55°C to +125°C Width of clock pulse (tCLK): Device types 08 and 09- - - - - - - - - - - - 27 ns minimum Setup time before clock (tsetup): Device types 08 and 09- - - - - - - - - - - - 30 ns minimum Hold time (thold): Device types 08 and 09- - - - - - - - - - - - 8 ns minimum Supply voltage (VCC)- - - - - - - - - - - - - 2 V dc to 6 V dc Output voltage- - - - - - - - - - - - - - - - 0 V dc to VCC Input rise and fall times (tr, tf) maximum: VCC = 2 V 1000 ns VCC = 4.5 V 500 ns VCC = 6 V 400 ns Device type 53: Input low (VIL) maximum voltage - - - - - - - 0.8 v at VCC = 4.5 V − 5.5 V Input high (VIH) minimum voltage- - - - - - - 2.0 V at VCC = 4.5 V − 5.5 V Supply voltage (VCC)- - - - - - - - - - - - - 4.5 V dc to 5.5 V dc Output voltage- - - - - - - - - - - - - - - - 0 V dc to VCC Operating ambient temperature TA- - - - - - - −55°C to +125°C Input rise and fall times (tr, tf): VCC = 4.5 V 500 ns maximum

intended Use:

Microcircuits conforming to this specification are intended for original equipment design application and logistic support of existing equipment.

Document History

November 26, 2019
Microcircuits, Digital, High Speed CMOS, Bus Transceivers with Three-State Outputs, Monolithic Silicon
A description is not available for this item.
February 13, 2015
Microcircuits, Digital, High Speed CMOS, Bus Transceivers with Three-State Outputs, Monolithic Silicon
A description is not available for this item.
May 6, 2010
Microcircuits, Digital, High Speed CMOS, Bus Transceivers with Three-State Outputs, Monolithic Silicon
This specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are...
July 22, 2005
MICROCIRCUITS, DIGITAL, HIGH-SPEED CMOS, BUS TRANSCEIVERS WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, high speed CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are...
January 8, 2003
MICROCIRCUITS, DIGITAL, HIGH-SPEED CMOS, BUS TRANSCEIVERS WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON
A description is not available for this item.
March 27, 1998
MICROCIRCUITS, DIGITAL, HIGH-SPEED CMOS, BUS TRANSCEIVERS WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON
A description is not available for this item.
August 9, 1996
MICROCIRCUITS, DIGITAL, HIGH-SPEED CMOS, BUS TRANSCEIVERS WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON
A description is not available for this item.
January 29, 1988
MICROCIRCUITS, DIGITAL, HIGH-SPEED CMOS, BUS TRANSCEIVERS WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON
A description is not available for this item.
MIL-M-38510/655
September 30, 1986
MICROCIRCUITS, DIGITAL, HIGH-SPEED CMOS, BUS TRANSCEIVERS WITH THREE-STATE OUTPUTS, MONOLITHIC SILICON
This specification covers the detail requirements for monolithic silicon, high speed, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are...

References

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