scope:

This document establishes the requirements and test procedures for the procurement of an electronic digital read only memory module.

The following electrical parameters reflect the 0° to 60°C end-of-life limits from table II.

Name Memory, read only Family Digital Key code As specified in 3.5.1 Size 1A Weight 35 grams maximum Failure rate 2.4 failures/10⁶ hours maximum Environment Class I as specified in MIL-M-28787 Maximum power dissipation 2.86 watts (outputs not loaded) Supply voltage 5 Vdc ±10 percent Input voltage Low level −0.5 V minimum, 0.8 V maximum High level 2.0 V minimum, V_cc maximum Input current, A10-A18, A20-A28 Low level (V_IL = 0.0 V) −0.88 mA maximum (V_IL = 0.45 V) −0.8 mA maximum High level (V_IH = 2.4 V) 80 µA maximum (V_IH = 5.5 V) 2.0 mA maximum Input current, E1 and E2 Low level (V_IL = 0.0 V) −0.88 mA maximum (V_IL = 0.45 V) −0.8 mA maximum High level (V_IH = 2.4 V) 80 µA maximum (V_IH = 5.5 V) 40 mA maximum (V_IH = 4.5 V) 2.0 mA maximum

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commander, Naval Electronic Systems Command, ATTN: ELEX 5043, Department of the Navy, Washington, D. C. 20360 by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Input clamp diode voltage −1.5 V maximum (V_cc = 4.5 V, I_Clamp = −5 mA) Output voltage Low level (I_OL = 8.0 mA) 0.5 V maximum High level (I_OH = ±900 µA) 2.4 V minimum Output drive current maximum capability Low level (V_OL = 0.5 V) 8.0 mA High level (V_OH = 2.4 V) −900 µA Disable output current Low level (V_OL = 0.5 V) ±100 µA maximum High level (V_OH = 2.4 V) ±100 µA maximum Input capacitance, A10-A18, A20-A28 30 p^F maximum Input capacitance, E1 and E2 35 p^F maximum Output capacitance, D10-D17, D20-D27 20 p^F maximum Dynamic characteristics (see figure 1) Propagation delay time t_AA - Address to data out, C_L = 50 p^F 95.0 ns maximum t_AA - Address to data out, C_L = 150 p^F 105.0 ns maximum t_EA - Enable/disable, C_L = 50 p^F 45.0 ns maximum t_EA - Enable/disable, C_L = 150 p^F 55.0 ns maximum Enable recovery time Low-state to high-impedance state (t_ERL), C_L = < 10 p^F 50 ns maximum High-state to high-impedance state (t_ERH), C_L = < 10 p^F 50 ns maximum

The read only memory module is a plug-in Standard Hardware Program (SHP) electronic module with 0.100 inch (2.54 mm) grid center contacts. The module is organized as two independent 512-word by 8-bit memories. These memories may be interconnected through connector wiring to form a memory of either 512 by 16 or 1024 by 8.

Each read only memory module has the input to output relationship of table I. The following describes the essential module operation. The module contains two independent 512-word by 8-bit read only memories as shown on figure 4. When the enable of one of the 512-word by 8-bit memories goes to the low level, the data stored at the selected address input appears at the eight data outputs of that memory. When the enable of one of the memories is high, the eight outputs of that memory are disabled to a high-impedance state.

Corresponding address inputs of the two address groups must be paralleled for nonindependent operation of the two memory sections.

The 512 by 16 organization is achieved by paralleling the corresponding addresses of the two sections and connecting both circuit enable lines together, as shown on figure 2.

The 1024 by 8 organization is achieved by paralleling the corresponding addresses of the two sections and the corresponding outputs of D10 through D17 with D20 through D27, as shown on figure 3.

A number of memory outputs can be connected to a common bus. All of the devices except one are placed in the high-impedance state, and the selected device is enabled. When outputs of several modules are bussed together, all address lines should be addressed using synchronous clocking. TABLE I. Input to output relationship.

E1 E2 Outputs --------------------------------------------- D10-D17 D20-D27 ---------------------------------------------------------- H H High Z High Z H L High Z Read data at A20-A28 L H Read data at A10-A18 High Z L L Read data at A10-A18 Read data at A20-A28 NOTES: 1. H = High-level input. 2. L = Low-level input. 3. High Z = High-impedance state.