scope:

This specification covers the detail requirements for silicon, monolithic, seven and eight gate, Darlington transistor array microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number.

The complete number shall be in accordance with MIL-M-38510.

The device types shall be as follows:

Device types Circuit 01, 02, 03, 04, 05 Darlington transistor array, seven gate 06, 07, 08, 09, 10 Darlington transistor array, eight gate

The device class shall be the product assurance level as defined in MIL-M-38510.

The case outlines shall be designated as follows:

Outline letter Case outline (see MIL-M-38510, appendix C) E D-2 (16-lead, ¼" × ⅞"), dual-in-line-package V D-6 (18-lead, ¼" × 15/16"), dual-in-line-package

Output voltage, (V_CE) - - - - - - - - - - - - 50 V dc Input voltage, (V_IN) Device types 02, 03, 04, 07, 08, 09 - - - - 30 V dc Device types 05, 10 - - - - - - - - - - - - 15 V dc Peak collector current (I_C) - - - - - - - - - 500 mA Peak input current (I_IN)- - - - - - - - - - - 25 mA Power dissipation (P_D) 1/ - - - - - - - - - - 1.0 W Storage temperature range - - - - - - - - - - −65°C to +150°C Junction temperature (T_J) - - - - - - - - - - +175°C.

Recommended operating conditions shall be in accordance with the electrical performance characteristics specified in table I.

Ambient operating temperature (T_A) - - - −55°C to +125°C

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Rome Air Development Center (RBE-2), Griffiss AFB, NY 13441, by using the self-addressed Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

Package Case Max. allowable Max. θ_JC Max. θ_JA outline power dissipation 16-lead, dual- E 277 mV at T_A = +125°C 20°C/W 90°C/W in-line package 18-lead, dual- V 330 mV at T_A = +125°C 20°C/W 75°C/W in-line package