ESD TR5.4-04
Electrostatic Discharge Sensitivity Testing Transient Latch-up Testing
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| Organization: | ESD |
| Publication Date: | 1 January 2013 |
| Status: | active |
| Page Count: | 67 |
scope:
INTRODUCTION
Definition
Transient latch-up (TLU) is defined as a state in which a low-impedance path, resulting from a transient overstress that triggers a parasitic thyristor structure or bipolar structure or combinations of both, persists at least temporarily after removal or cessation of the triggering condition. The rise time of the transient overstress causing TLU is shorter than five μs.1 TLU as defined in this document does not cover changes of functional states, even if those changes would result in a low-impedance path and increased power supply consumption.
Document History
ESD TR5.4-04
January 1, 2013
Electrostatic Discharge Sensitivity Testing Transient Latch-up Testing
INTRODUCTION
Definition
Transient latch-up (TLU) is defined as a state in which a low-impedance path, resulting from a transient overstress that triggers a parasitic thyristor structure or bipolar...