ESD SP5.4.1

Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level

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Organization: ESD
Publication Date: 20 September 2017
Status: active
Page Count: 28
scope:

This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients.

Purpose

This document addresses steps which are required to perform transient latch-up (TLU) characterization under well-defined conditions. It defines pre-conditioning of the device-under-test (DUT), applying the stress pulse, detecting latch-up, and determining failure criteria. Additionally, a procedure to verify the test equipment is described. The test methods enable the user to perform an application specific TLU characterization with reliable and verified test set-ups.

Application

This document defines a characterization methodology which is intentionally kept as flexible as possible. This document does not define a qualification standard.

The characterization can be applied to:

• Test structures (for example, process assessment, component verification).

• Distinct pins of products (stand-alone and with "simple" external circuitries).

• I/O pins of systems and subsystems.

• Integrated circuits with or without external circuitry which is typical for the application or required for pre-conditioning the IC. The IC might be mounted on a printed-circuit board (PCB).

In order to perform the TLU test one has to define the pins under test and the testing parameters.

This document is intended to be a guideline for the application engineer who defines the test and the test engineer who performs the test according to the definition and prepares a report. The characterization is application specific. Hence, the focus of this document is on the general methodology and particularly on verification of the methodology.

TLU as defined in this document does not cover changes of functional states, even if those changes would result in a low-impedance path and increased power supply consumption.

Document History

ESD SP5.4.1
September 20, 2017
Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level
This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients. Purpose This document addresses steps which are required to perform...

References

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