ESD TR5.4-03
Electrostatic Discharge Sensitivity Testing Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
| Organization: | ESD |
| Publication Date: | 1 January 2011 |
| Status: | active |
| Page Count: | 36 |
scope:
This technical report describes a procedure for measuring latch-up sensitivity of integrated circuits to transients on power supply lines. Circuits on which this test method may be applied include CMOS (Complementary Metal Oxide Semiconductor), Bipolar, and BiCMOS (Bipolar- CMOS) devices typically requiring less than 30 volts for operation. The range of integrated circuits on which this procedure has been shown to be useful is limited.
Purpose
The information and procedures defined in this technical report may be used to search for latchup sensitive layouts within integrated circuits. The stress levels and stimuli parameter values defined may be used for a wide range of devices. Levels and values can be scaled up or down to suit the requirements of the actual device under test and types of transient stimuli being used.
Document History
