JEDEC JESD 78
IC Latch-Up Test
|Publication Date:||1 April 2016|
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits.
The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latchup. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
NOTE As these technologies have evolved, it has been necessary to adjust this document to the realities of characterization with limits not imagined when the first latch-up document was generated some 25 years ago. Though it would be simpler to make the original limits of 1.5 times the maximum pin operating voltage an absolute level of goodness, the possibilities of success at this level are limited by the very low voltage technologies, and the medium and high voltage CMOS, BiCMOS and Bipolar technologies (>12 V). The concept of maximum stress voltage (MSV) allows the supplier to characterize latch-up in a way that differentiates between latch-up and EOS. This revision will make it more transparent to the end user that given the limits of certain technologies the subsequent latch-up characterizations are valid.