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JEDEC JESD 78

IC Latch-Up Test

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Organization: JEDEC
Publication Date: 1 September 2010
Status: inactive
Page Count: 28
scope:

This specification covers the I-test and the overvoltage latch-up testing of integrated circuits.

The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.

Classification

There are two classes for latch-up testing.

• Class I is for testing at room temperature ambient.

• Class II is for testing at the maximum operating ambient temperature (Ta) or maximum operating case temperature (Tc) or maximum operating junction temperature (Tj) in the data sheet.

For Class II testing at the maximum operating Ta or Tc, the ambient temperature or case temperature (Tc) shall be established at the required test value. For Class II testing at the maximum operating Tj, the ambient temperature Ta or the case temperature Tc should be selected to achieve a temperature characteristic of the junction temperature for a given device operating mode(s) during latch-up testing. The maximum operating ambient or case temperature during stress may be calculated based on the methods detailed in Annex B. The values used in Class II testing shall be recorded in the final report.

NOTE Elevated temperature will reduce latch-up resistance, and class II testing is recommended for devices that are required to operate at elevated temperature.

Level

Level defines the I-test current injection value used during latch-up testing. Latch-up passing levels are defined as follows:

Level A - The trigger current value in Table 1 shall be +100 mA as defined in Figure 5 and -100 mA as defined in Figure 6. If all pins on the part pass at least the Level A trigger current values, then the part shall be considered a Level A part.

Level B - If any pins on the part do not pass the Level A standard, then the supplier shall determine the minimum passing trigger current requirement for each pin stressed differently than in Level A. The maximum (or highest) passing trigger current value shall be reported in the record for each pin stressed differently than in Level A, and the part shall be considered to be a Level B part, see 4.2.5.

Document History

November 1, 2023
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
December 1, 2022
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
January 1, 2022
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
April 1, 2016
IC Latch-Up Test
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and...
November 1, 2011
IC Latch-Up Test
This standard covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics...
JEDEC JESD 78
September 1, 2010
IC Latch-Up Test
This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up...
December 1, 2008
IC Latch-Up Test
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard establishes a defined method for latch-up testing of ICs. It defines Classes and Levels for a...
February 1, 2006
IC Latch-Up Test
This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. Purpose The purpose of this specification is to establish a method for determining IC latch-up...
March 1, 1997
IC Latch-Up Test
A description is not available for this item.

References

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