JEDEC - JESD78F
IC Latch-Up Test
Organization: | JEDEC |
Publication Date: | 1 January 2022 |
Status: | inactive |
Page Count: | 86 |
scope:
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard covers a current-injection test (Signal Pin Test) and an overvoltage test (Supply Test). Current injection is achieved either by current forcing with voltage compliance limit (I-Test) or by applying voltage with current compliance limit (E-Test).
All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. [This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies including Silicon-On-Insulator
Purpose
The purpose (objective) of this standard is to establish a test method that will replicate latch-up failures during device operation and provide reliable, repeatable latch-up test results from tester to tester, regardless of device type. Repeatable data will allow accurate classifications and comparisons of latch-up sensitivity levels. The document will also provide guidelines to allow the user to apply engineering judgement when historical testing methods are not compatible with the integrated circuit's functionality.
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