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JEDEC - JESD78F.01

IC Latch-Up Test

inactive
Organization: JEDEC
Publication Date: 1 December 2022
Status: inactive
Page Count: 94
scope:

This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard covers a current-injection test (Signal Pin Test) and an overvoltage test (Supply Test). Current injection is achieved either by current forcing with voltage compliance limit (I-Test) or by applying voltage with current compliance limit (E-Test).

All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies including some Silicon-On-Insulator (SOI).

Purpose

The purpose (objective) of this standard is to establish a test method that will replicate latch-up failures during device operation and provide reliable, repeatable latch-up test results from tester to tester, regardless of device type. Repeatable data will allow accurate classifications and comparisons of latch-up sensitivity levels. The document will also provide guidelines to allow the user to apply engineering judgement when historical testing methods are not compatible with the integrated circuit's functionality.

Document History

November 1, 2023
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
JESD78F.01
December 1, 2022
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
January 1, 2022
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
April 1, 2016
IC Latch-Up Test
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and...
November 1, 2011
IC Latch-Up Test
This standard covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics...
September 1, 2010
IC Latch-Up Test
This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up...
December 1, 2008
IC Latch-Up Test
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard establishes a defined method for latch-up testing of ICs. It defines Classes and Levels for a...
February 1, 2006
IC Latch-Up Test
This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. Purpose The purpose of this specification is to establish a method for determining IC latch-up...
March 1, 1997
IC Latch-Up Test
A description is not available for this item.

References

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