UNLIMITED FREE
ACCESS TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Select Your Free Newsletters

Industry Newsletters

Select Your Free Product Alerts

Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

JEDEC JESD 78

IC Latch-Up Test

inactive
Buy Now
Organization: JEDEC
Publication Date: 1 December 2008
Status: inactive
Page Count: 28
scope:

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard establishes a defined method for latch-up testing of ICs. It defines Classes and Levels for a device's latch-up capability so that both the user and supplier understand a device's latch-up capabilities. It is applicable to NMOS, CMOS, Bipolar, and all variations and combinations of these technologies. Latch-up is an extremely important factor in determining product reliability. This document contains the corrected figure 4 to include T6 on page 12, this change was made in January 1998.

Document History

JESD78F.02
November 1, 2023
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
JESD78F.01
December 1, 2022
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
JESD78F
January 1, 2022
IC Latch-Up Test
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to...
JEDEC JESD 78
April 1, 2016
IC Latch-Up Test
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and...
JEDEC JESD 78
November 1, 2011
IC Latch-Up Test
This standard covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics...
JEDEC JESD 78
September 1, 2010
IC Latch-Up Test
This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up...
JEDEC JESD 78
December 1, 2008
IC Latch-Up Test
This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This standard establishes a defined method for latch-up testing of ICs. It defines Classes and Levels for a...
JEDEC JESD 78
February 1, 2006
IC Latch-Up Test
This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. Purpose The purpose of this specification is to establish a method for determining IC latch-up...
JEDEC JESD 78
March 1, 1997
IC Latch-Up Test
A description is not available for this item.
View Less
View All

References

This document is referenced by:
SMD 5962-10208 - MICROCIRCUIT, DIGITAL, ASIC, RADIATION HARDENED, SOI CMOS, SERIALIZER/DESERIALIZER (SERDES), MONOLITHIC SILICON
Published by DOD on September 1, 2010
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes...
This document is referenced by:
SMD 5962-92201 - MICROCIRCUIT, DIGITAL, ADVANCED CMOS, NINE-BIT PARITY GENERATOR/CHECKER, MONOLITHIC SILICON
Published by DOD on November 29, 2017
This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead finishes are...
This document is referenced by:
SMD 5962-06229 - MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 16 MBIT (512K X 32), RADIATION-HARDENED, LOW VOLTAGE SRAM, MULTICHIP MODULE
Published by DOD on September 18, 2018
This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are...
This document is referenced by:
SMD 5962-10205 - MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 1MEG X 39-BIT (40M), RADIATION-HARDENED, DUAL VOLTAGE SRAM, MULTICHIP MODULE
Published by DOD on November 2, 2020
Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes...
This document is referenced by:
SMD-5962-92183 REV F - MICROCIRCUIT, DIGITAL, ADVANCED CMOS, HEX INVERTER WITH SCHMITT TRIGGER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON
Published by DLA on October 25, 2022
Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q and M) and space application (device class V). A choice of case outlines and lead...
View Less
View All

Related Products

Searching for related products...

Advertisement