JEDEC JESD 78
IC Latch-Up Test
Organization: | JEDEC |
Publication Date: | 1 February 2006 |
Status: | inactive |
Page Count: | 30 |
scope:
This specification covers the I-test and the overvoltage latch-up testing of integrated circuits.
Purpose
The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.
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