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ESD - SP5.4.1

Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level

active, Most Current
Organization: ESD
Publication Date: 20 June 2022
Status: active
Page Count: 31
scope:

This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients.

Purpose

This document addresses the steps required to perform transient latch-up (TLU) characterization under well-defined conditions. It defines preconditioning of the device-under-test (DUT), applying the stress pulse, detecting latch-up, and determining failure criteria. Additionally, a procedure to verify the test equipment is described. The test methods enable the user to perform an application specific TLU characterization with reliable and verified test set-ups.

Document History

SP5.4.1
June 20, 2022
Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level
This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients. Purpose This document addresses the steps required to perform...
ESD SP5.4.1
September 20, 2017
Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing Device Level
This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients. Purpose This document addresses steps which are required to perform...

References

This document references:
ESD ADV1.0 - Electrostatic Discharge Terminology Glossary
Published by ESD on January 31, 2017
This document contains unified definitions and explanations of terminology used in the standards, standard practices, standard test methods, technical reports, and other documents of EOS/ESD...
This document references:
ESD S20.20 - the Development of an Electrostatic Discharge Control Program for - Protection of Electrical and Electronic Parts, Assemblies, and Equipment (Excluding Electrically Initiated Explosive Devices)
Published by ESD on June 11, 2014
This document applies to activities that manufacture, process, assemble, install, package, label, service, test, inspect, transport or otherwise handle electrical or electronic parts, assemblies and...
This document references:
ESD SP5.2 - Electrostatic Discharge Sensitivity Testing – Machine Model (MM) – Component Level
Published by ESD on February 22, 2019
This document establishes the procedure for testing and characterizing the electrostatic discharge (ESD) sensitivity (withstand voltage) of components subjected to the defined machine model (MM)....
This document references:
ESD STM5.5.1 - Electrostatic Discharge Sensitivity Testing – Transmission Line Pulse (TLP) – Device Level
Published by ESD on November 2, 2016
The scope and focus of this document pertains to TLP testing techniques of semiconductor components. The focus of the document is on quasi-static application of TLP testing techniques, however the...
This document references:
ESD TR5.4-03 - Electrostatic Discharge Sensitivity Testing Latch-Up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits Transient Latch-up Testing – Component Level Supply Transient Stimulation
Published by ESD on January 1, 2011
This technical report describes a procedure for measuring latch-up sensitivity of integrated circuits to transients on power supply lines. Circuits on which this test method may be applied include...
This document references:
ESD TR5.4-04 - Electrostatic Discharge Sensitivity Testing Transient Latch-up Testing
Published by ESD on January 1, 2013
INTRODUCTION Definition Transient latch-up (TLU) is defined as a state in which a low-impedance path, resulting from a transient overstress that triggers a parasitic thyristor structure or bipolar...
This document references:
IEC 61000-4-2 - Electromagnetic compatibility (EMC) – Part 4-2: Testing and measurement techniques – Electrostatic discharge immunity test
Published by IEC on December 1, 2008
This International Standard relates to the immunity requirements and test methods for electrical and electronic equipment subjected to static electricity discharges, from operators directly, and to...
This document references:
IEC 61340-5-1 - Electrostatics – Part 5-1: Protection of electronic devices from electrostatic phenomena – General requirements
Published by IEC on May 1, 2016
This part of IEC 61340 applies to activities that: manufacture, process, assemble, install, package, label, service, test, inspect, transport or otherwise handle electrical or electronic parts,...
This document references:
JESD625C - Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices
Published by JEDEC on October 1, 2022
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). Processes that include items...
This document references:
JEDEC JESD 78 - IC Latch-Up Test
Published by JEDEC on April 1, 2016
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and...
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