JEDEC JESD 22-A122
|Publication Date:||1 June 2016|
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. This specification covers power induced temperature cycling of a packaged component, simulating the non-uniform temperature distribution resulting from a device powering on and off in the application.
This test is conducted to determine the ability of solid state device to withstand thermal-mechanical stresses induced by cyclic, non-isothermal high and low temperatures induced by the device operation, including options like standby, hibernate or mini cycles found in some applications. It is used to verify the performance of various component materials and interfaces, especially solder interconnects and thermal interface materials (TIM). Both engineering samples with internal or external thermal heaters and actual power driven product can be used in this test method. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses and as such should be considered a destructive test.