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DLA - DSCC-VID-V62/03668 REV C

MICROCIRCUIT, DIGITAL, CMOS, EMBEDDED TEST-BUS CONTROLLER, IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES, MONOLITHIC SILICON

active, Most Current
Organization: DLA
Publication Date: 26 May 2020
Status: active
Page Count: 18
scope:

Scope.

This drawing documents the general requirements of a high performance embedded test-bus controller, IEEE Std 1149.1 (JTAG) TAP masters with 8-bit generic host interfaces microcircuit, with an operating temperature range of -40°C to +85°C.

Document History

DSCC-VID-V62/03668 REV C
May 26, 2020
MICROCIRCUIT, DIGITAL, CMOS, EMBEDDED TEST-BUS CONTROLLER, IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES, MONOLITHIC SILICON
Scope. This drawing documents the general requirements of a high performance embedded test-bus controller, IEEE Std 1149.1 (JTAG) TAP masters with 8-bit generic host interfaces microcircuit, with an...
DSCC-VID-V62/03668 REV B
December 22, 2014
MICROCIRCUIT, DIGITAL, CMOS, EMBEDDED TEST-BUS CONTROLLER, IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance embedded test-bus controller, IEEE Std 1149.1 (JTAG) TAP masters with 8-bit generic host interfaces microcircuit, with an...
DSCC-VID-V62/03668 REV A
March 12, 2008
MICROCIRCUIT, DIGITAL, CMOS, EMBEDDED TEST-BUS CONTROLLER, IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES, MONOLITHIC SILICON
This drawing documents the general requirements of a high performance embedded test-bus controller, IEEE Std 1149.1 (JTAG) TAP masters with 8-bit generic host interfaces microcircuit, with an...
DSCC-VID-V62/03668
November 3, 2003
MICROCIRCUIT, DIGITAL, CMOS, EMBEDDED TEST-BUS CONTROLLER, IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES, MONOLITHIC SILICON
A description is not available for this item.

References

This document references:
IEEE 1149.1 - Test Access Port and Boundary-Scan Architecture
Published by IEEE on February 6, 2013
This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to: - Testing the interconnections between integrated circuits once they have been...
This document references:
JEP95 BOOK 1 - Book One Registered and Standard Outlines for Solid State and Related Products
Published by JEDEC on March 1, 1997
PREFACE This Publication contains those solid state product outlines and other associated drawings that have been registered and assigned a JEDEC designation and are printed on white paper. Product...
This document references:
JEP95 BOOK 2 - Registered and Standard Outlines for Solid State and Related Products
Published by JEDEC on March 1, 1997
A description is not available for this item.
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