scope:

This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the systems space and the verification space. SystemVerilog is built on top of IEEE Std 1364 1 for the Verilog HDL. This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI). Throughout this standard, the following terms apply: - Verilog refers to IEEE Std 1364 for the Verilog HDL. - Verilog-2001 refers to IEEE Std 1364-2001 [B4]2 for the Verilog HDL. - Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL. - SystemVerilog refers to the extensions to the Verilog standard (IEEE Std 1364) as defined in this standard.