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NEN-IEC 62530

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

active, Most Current
Organization: NEN
Publication Date: 1 August 2021
Status: active
Page Count: 1,324
ICS Code (Languages used in information technology): 35.060
ICS Code (Industrial automation systems in general): 25.040.01
scope:

This standard provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.

Purpose

This standard develops the IEEE 1800 SystemVerilog language in order to meet the increasing usage of the language in specification, design, and verification of hardware. This revision corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.

1Information on references can be found in Clause 2.

Document History

NEN-IEC 62530
August 1, 2021
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
This standard provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The...
NEN-IEC 62530
July 1, 2011
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
This SystemVerilog standard (IEEE Std 1800) is a Unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by...
NEN-IEC 62530
December 1, 2007
Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
This standard specifies extensions for a higher level of abstraction for modeling and verification with the Verilog® hardware description language (HDL). These additions extend Verilog into the...

References

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This document references:
IEEE 1364 - Standard Verilog Hardware Description Language
Published by IEEE on January 1, 2005
Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously...
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IEEE 61523-3 - Delay and power calculation standards Part 3: Standard Delay Format (SDF) for the electronic design process
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A description is not available for this item.
This document references:
IEEE 1800 - Errata to IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
Published by IEEE on April 15, 2019
A description is not available for this item.
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This document specifies dedicated hash-functions, i.e. specially designed hash-functions. The hashfunctions in this document are based on the iterative use of a round-function. Distinct...
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ISO/IEC 9899 - Information technology - Programming languages - C
Published by ISO on July 1, 2018
This document specifies the form and establishes the interpretation of programs written in the C programming language.1) It specifies — the representation of C programs; — the syntax and constraints...
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IEEE 1735 - Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)
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This standard specifies embeddable and encapsulating markup syntaxes for design intellectual property encryption and rights management, together with recommendations for integration with design...
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