scope:

This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document.

Due to the range of applications involved, the intention of this standard is to completely specify only the serial data interface and the link protocol. Devices may have application-dependent modes, such as a low power / shutdown mode that will affect the interface. In these instances, the specification merely constrains other device properties as they relate to the interface and leaves the specific implementation up to the designer.

Revision D of the standard supports the following functions:

• Data interfaces up to 116 Gbps with PAM4 encoding and up to 58 Gbps with PAM2 (NOTE) encoding.

• The standard supports three types of channels, Extra Short Reach Interface, (XSR), Mid Reach Interface, (MR,) and Long Reach Interface, (LR).

• RS-FEC link layer (not backward compatible with previous JESD204 revisions)

NOTE This standard uses the term PAM2 as a synonym for NRZ.

Figure 2 compares the scope of the original JESD204 specification and its revisions. Although not illustrated in the figure, it is possible to apply multiple, independent instances of the JESD204 standard to the same device. The logic device (e.g., ASIC or FPGA) is always assumed to be a single device.