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JEDEC JESD 8-5

2.5 V (PLUS OR MINUS) 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits

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Organization: JEDEC
Publication Date: 1 September 2007
Status: active
Page Count: 14
scope:

This standard defines power supply voltage ranges, dc interface parameters for a high speed, low voltage family of non-terminated digital circuits driving/driven by parts of the same family. The specifications in this standard represent a minimum set of 'base line' set of interface specifications for CMOS-compatible circuits.

Document History

JEDEC JESD 8-5
September 1, 2007
2.5 V (PLUS OR MINUS) 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits
This standard defines power supply voltage ranges, dc interface parameters for a high speed, low voltage family of non-terminated digital circuits driving/driven by parts of the same family. The...
JEDEC JESD 8-5
June 1, 2006
2.5 V (PLUS OR MINUS) 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits
A description is not available for this item.
JEDEC JESD 8-5
January 1, 1995
2.5V +/- 0.2V (Normal Range), and 1.8V to 2.7V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit
A description is not available for this item.

References

This document is referenced by:
BS IEC 60748-2-20 - Semiconductor devices - Integrated circuits - Part 2-20: Digital integrated circuits - Family specification - Low voltage integrated circuits
Published by BSI on September 30, 2008
A description is not available for this item.
This document is referenced by:
SMD-5962-16208 REV G - MICROCIRCUIT, MEMORY, DIGITAL, CMOS, LOW POWER REPROGRAMMABLE 151,824 LOGIC ELEMENT FLASH FIELD PROGRAMMABLE GATE ARRAY WITH DECOUPLING CAPACITORS, MONOLITHIC SILICON
Published by DLA on November 2, 2023
A description is not available for this item.
This document is referenced by:
ISO 21111-2 - Road vehicles — In-vehicle Ethernet — Part 2: Common physical entity requirements
Published by ISO on October 1, 2020
This document specifies the following items to complement ISO/IEC /IEEE 8802-3: — interface between reconciliation sublayer and physical entity including reduced gigabit media independent interface...
This document is referenced by:
BS ISO 21111-2 - Road vehicles — In-vehicle Ethernet Part 2: Common physical entity requirements
Published by BSI on November 30, 2020
A description is not available for this item.
This document is referenced by:
JEDEC JESD 82-6 - Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications
Published by JEDEC on November 1, 2004
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked...
This document is referenced by:
JEDEC JESD 82-13 - Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700 and PC3200 DDR DIMM Applications
Published by JEDEC on May 1, 2005
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTVN16859 13-bit to 26-bit SSTL_2 registered buffer for PC1600,...
This document is referenced by:
JESD204D - Serial Interface for Data Converters
Published by JEDEC on December 1, 2023
This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other...
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