JEDEC JESD 8-22
HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT
active, Most Current
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| Organization: | JEDEC |
| Publication Date: | 1 April 2014 |
| Status: | active |
| Page Count: | 38 |
scope:
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages.
Document History
JEDEC JESD 8-22
April 1, 2014
HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally...
October 1, 2012
HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally...
August 1, 2009
HSUL_12 LPDDR2 I/O
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally...