scope:

This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device classes M and Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment

The PIN shall be as shown in the following example:

Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

The device type(s) shall identify the circuit function as follows:

Device DM Generic number Circuit function 01 ACT3641 1K × 36 clocked FIFO

The device class designator shall be a single letter identifying the product assurance level as follows:

Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A N Certification and qualification to MIL-PRF-38535 with a non-traditional performance environment 1/ Q or V Certification and qualification to MIL-PRF-38535

The case outline(s) are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X See figure 1 120 Plastic quad flat package Y See figure 1 132 Ceramic quad flat package

The lead finish is as specified in MIL-PRF-38535 for device classes N, Q, and V or MIL-PRF-38535, appendix A for device class M.

Lead finish D shall be designated by a single letter as follows:

Finish letter Process D Palladium

Supply voltage range (V_CC) ......................................... −0.5 V dc to +7.0 V dc DC input voltage range (I/O ports) (V_IN) ........................... −0.5 V dc to V_CC + 0.5 V dc 5/ DC output voltage range (V_OUT) ..................................... −0.5 V dc to V_CC + 0.5 V dc 5/ DC output current (I_O) (per output)(V_O = 0.0 to V_CC) ............... ±50 mA DC input clamp current (I_IK) (V_IN < 0.0 V or V_IN > V_CC) ............ ±20 mA DC output clamp current(I_OK)(V_OUT < 0.0 V or V_OUT > V_CC) ........... ±50 mA Storage temperature range (T_STG) ................................... −65°C to +150°C Lead temperature (soldering, 10 seconds) ........................... +300°C Thermal resistance, junction-to-case (Θ_JC) ......................... 3.3°C/W Junction temperature (T_J) .......................................... +175°C Maximum power dissipation (P_D) ..................................... 314 mW 6/ V_CC current (I_VCC) ................................................. ±400 mA Ground current(I_GND) ............................................... ±400 mA

Supply voltage range (V_CC) ......................................... +4.5 V dc to +5.5 V dc Maximum low level input voltage (V_IL) .............................. +0.8 V Minimum high level input voltage (V_IH) ............................. +2.0 V Maximum high level output (I_OH) .................................... −4.0 mA Maximum low level output current (I_OL) ............................. +8.0 mA Case operating temperature range (T_C) .............................. −55°C to + 125°C

Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) ....................... XX percent 7/

intended Use: