DLA - SMD-5962-97545 REV A
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512K X 16-BIT X 2-BANK, SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM), MONOLITHIC SILICON
| Organization: | DLA |
| Publication Date: | 20 January 1998 |
| Status: | inactive |
| Page Count: | 53 |
scope:
This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device classes M and Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment.
Functional algorithms are test patterns which define the exact sequence of events used to verify proper operation of a random access memory(RAM). Each algorithm serves a specific purpose for the testing of the device. It is understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be applied to the device in a topologically pure fashion. This Appendix is a mandatory part of the specification. The information contained herein is intended for compliance.
intended Use:
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications(origina
Microcircuits... View More
Document History