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DLA - SMD-5962-87002 REV D

MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON

inactive
Organization: DLA
Publication Date: 6 September 1994
Status: inactive
Page Count: 32
scope:

This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices".

The complete PIN shall be as shown in the following example:

The device type(s) shall identify the circuit function as follows:

Device type Generic number Circuit function Access time 01 7132SA 2K × 8 dual port static RAM, MASTER 45 ns 02 7132SA 2K × 8 dual port static RAM, MASTER 90 ns 03 7132SA 2K × 8 dual port static RAM, MASTER 70 ns 04 7132SA 2K × 8 dual port static RAM, MASTER 55 ns 05 7132LA 2K × 8 dual port static RAM, MASTER 45 ns 06 7132LA 2K × 8 dual port static RAM, MASTER 90 ns 07 7132LA 2K × 8 dual port static RAM, MASTER 70 ns 08 7132LA 2K × 8 dual port static RAM, MASTER 55 ns 09 7142SA 2K × 8 dual port static RAM, SLAVE 45 ns 10 7142SA 2K × 8 dual port static RAM, SLAVE 90 ns 11 7142SA 2K × 8 dual port static RAM, SLAVE 70 ns 12 7142SA 2K × 8 dual port static RAM, SLAVE 55 ns 13 7142LA 2K × 8 dual port static RAM, SLAVE 45 ns 14 7142LA 2K × 8 dual port static RAM, SLAVE 90 ns 15 7142LA 2K × 8 dual port static RAM, SLAVE 70 ns 16 7142LA 2K × 8 dual port static RAM, SLAVE 55 ns 17 7132SA 2K × 8 dual port static RAM, MASTER 35 ns 18 7132LA 2K × 8 dual port static RAM, MASTER 35 ns 19 7132SA 2K × 8 dual port static RAM, MASTER 25 ns 20 7132LA 2K × 8 dual port static RAM, MASTER 25 ns 21 7142SA 2K × 8 dual port static RAM, SLAVE 35 ns 22 7142LA 2K × 8 dual port static RAM, SLAVE 35 ns 23 7142SA 2K × 8 dual port static RAM, SLAVE 25 ns 24 7142LA 2K × 8 dual port static RAM, SLAVE 25 ns

The case outline(s) shall be as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style X CQCC1-N52 52 square leadless chip carrier Y See figure 1 48 dual-in-line Z GDIP1-T48 or CDIP2-T48 48 dual-in-line U See figure 1 48 square leadless chip carrier T See figure 1 48 flat pack

The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein). Finish letter "X" shall not be marked on the microcircuit or its packaging. The "X" designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference.

Voltage on any pin with respect to ground 1/ - - - - −0.5 V to +7.0 V Storage temperature range- - - - - - - - - - - - - - −65°C to +150°C

Power dissipation (PD) - - - - - - - - - - - - - - - 1 W Lead temperature (soldering, 5 seconds)- - - - - - - +270°C Maximum junction temperature (TJ) 2/ - - - - - - - - +150°C Thermal resistance, junction-to-case (θJC): Cases X and Z - - - - - - - - - - - - - - - - - - See MIL-STD-1835 Case Y - - - - - - - - - - - - - - - - - - - - - - 23°C/W 3/ Case U - - - - - - - - - - - - - - - - - - - - - - 24°C/W 3/ Case T - - - - - - - - - - - - - - - - - - - - - - 20°C/W 3/ Maximum dc output current- - - - - - - - - - - - - - 50 mA

Case operating temperature range (TC)- - - - - - - - −55°C to +125°C Input low voltage (VIL)- - - - - - - - - - - - - - - −0.5 to +0.8 V dc 4/ Input high voltage (VIH) - - - - - - - - - - - - - - +2.2 V to VCC +0.5 V dc 4/ Supply voltage (VCC) - - - - - - - - - - - - - - - - +4.5 V to +5.5 V dc 4/

intended Use:

Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.

Document History

July 28, 2021
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A.
April 3, 2015
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
August 16, 2006
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes.
SMD-5962-87002 REV D
September 6, 1994
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices"....
August 27, 1990
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices"....
January 22, 1990
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
A description is not available for this item.
August 1, 1988
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
A description is not available for this item.
January 19, 1988
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON
A description is not available for this item.

References

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