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JEDEC JESD 8-9

Stub Series Terminated Logic for 2.5 Volts (SSTL_2)

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Organization: JEDEC
Publication Date: 1 May 2002
Status: active
Page Count: 30
scope:

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs.

Document History

JEDEC JESD 8-9
May 1, 2002
Stub Series Terminated Logic for 2.5 Volts (SSTL_2)
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be...
May 1, 2002
Stub Series Terminated Logic for 2.5 Volts (SSTL_2)
A description is not available for this item.
September 1, 1998
Stub Series Terminated Logic for 2.5 Volts (SSTL_2)
A description is not available for this item.

References

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